AMD pushing SSE5!!!

[Mitch101]

http://amdzone.com/modules.php...thread&order=0&thold=0

I dont really know what to say other than talk about a gutsy move of AMD acting as if they are the leaders of SSE. Heck I guess they might as well since Intel claimed they developed x84-64bit when it was actually AMD64.

You have to admire them for this.

 

[RussianSensation]

"The SSE5 specification, which is being made available to the developer community today at http://developer.amd.com/SSE5, will be implemented in products based on AMD?s next-generation ?Bulldozer? core, available in 2009."

Source

Wake me up in 2009...

 

[bryanW1995]

if phenom isn't the hoped-for savior then there might not be much of a need for sse5 or anything else related to amd by 2009.

 

[Mitch101]

I think that chapter 11 statement is overdone.

Its pretty clear that AMD should receive a large settlement from the lawsuit against Intel and phenom has a lot of support from third party vendors including a lot of server end companies who know the real benefit of these chips. AMD is also tapping into a lot of markets no one saw before and the ATI division of the company is pulling in cash even when the CPU portion isnt.

The AMD/Phenom cpu will deliver especially in multi cpu architectures as well as the GPU side of things will do well.

I would suspect NVIDIA 2 years from now will be in much bigger trouble than AMD/ATI.

 

[ForumMaster]

sounds to me like the OP is an AMD Fan-boy. dude, I'm posting from my beloved athlon xp-m 2400+ oc'ed to hell and as much as i like AMD, they are Hemorrhaging and if they don't get their act together, there won't be an AMD in 2009. also, the ATi has been losing market share ever since AMD bought them and this has caused a situation where nvidia has a monopoly in the discrete graphics market simply because their competitor was bought out.

I'm happy to see AMD pioneer an instruction set. nevertheless, unless Intel adopts it, no one will. i suggest you read AnandTech's article on the subject if you haven't already. While SSE5 looks like it might indeed be worthwhile, AMD not including full SSE4 support in Bulldozer is a stupid decision. I hope for competition's sake that AMD recovers. competition is good for the market.

 

[her34]

the next press release will cover:

geforce 10800xt crossfire edition

 

[ahock]

what if Intel will release SSE5 in Nehalem processor? I gues they will have since its a new architecture..... My take SSE is already for Intel although they are open standard. AMD should name it otherwise and prove to the industry that what they develop is worthwhile. This is to avoid confusion on the said instructions. Bad thing is SSE5 AMD is proposing are not backward compatible with most of SSE4. Tsk tsk tsk......

 

[Keysplayr]

Actually, I'm seeing more and more activity from AMD these past 2 weeks. They may be finally ready to get rolling. It all depends on just "how well" they kept their secret. muwahahahahahahhhaaaaaaa.......

 

[Keysplayr]

Originally posted by: ahock
what if Intel will release SSE5 in Nehalem processor? I gues they will have since its a new architecture..... My take SSE is already for Intel although they are open standard. AMD should name it otherwise and prove to the industry that what they develop is worthwhile. This is to avoid confusion on the said instructions. Bad thing is SSE5 AMD is proposing are not backward compatible with most of SSE4. Tsk tsk tsk......

You mean something like "3DNow"? Or 3DLater... sorry, it was so there.

 

[ahock]

yes something like 3DNow. I love AMD to participate in any of this development initiatives but naming SSE5? tsk tsk tsk

And why cant they have this backward compatible? It will be very very confusing to software developers. Likewise if Intel will release SSE5 before AMD now what?

 

[covert24]

what is SSE5 supposed to accomplish? what type of instructions does this have in relation to SSE4?

 

[Acanthus]

Originally posted by: covert24
what is SSE5 supposed to accomplish? what type of instructions does this have in relation to SSE4?

It's basically "we didnt implement all of SSE4, so we will just tack on some of our own code that doesnt do much and call it SSE5".

In my eyes :thumbsdown:

 

[CTho9305]

Originally posted by ahock
And why cant they have this backward compatible? It will be very very confusing to software developers. Likewise if Intel will release SSE5 before AMD now what?

In what way is it not "backwards compatible"? It's new instructions. There's no rule that says "if you support an instruction set extension released in year x you have to support all extensions released in years < x". There's a feature bit per extension - it's not a field that says "max SSE supported" or something like that.

Originally posted by covert24

what is SSE5 supposed to accomplish? what type of instructions does this have in relation to SSE4?

Did you even READ the link?

 

[adairusmc]

Originally posted by: Mitch101


Its pretty clear that AMD should receive a large settlement from the lawsuit against Intel

:laugh:

 

[SickBeast]

Originally posted by: Mitch101
I would suspect NVIDIA 2 years from now will be in much bigger trouble than AMD/ATI.

What's your reason for suspecting this? The lack of an X86 licence? The fact that the discreet graphics market might die off?

I don't think an X86 licence is that hard to come by; even VIA has one.

Further to that, the discreet graphics market is going nowhere, especially at the high end, and that's exactly where nVidia is dominiating right now. They also make awesome chipsets and support the OpenGL market like no other. They aren't going anywhere, and IMO a large company like IBM would be wise to gobble them up.

 

[SickBeast]

Originally posted by: adairusmc

Originally posted by: Mitch101


Its pretty clear that AMD should receive a large settlement from the lawsuit against Intel

:laugh:

What's so absurd about that? Intel is known to have strongarmed the chipset and motherboard partners to avoid building AMD parts. IMO AMD *should* be compensated for that. We can't have large corporations behaving in this way. They're already more powerful than any government on earth. :light:

 

[pm]

Doesn't Core 2 Duo achieve something similar to a 3 operand FMAC instruction by using macro-op fusion?

This is a serious question by the way. I am not any kind of microprocessor architect type person and don't pretend to be.

 

[tatteredpotato]

Originally posted by: Acanthus

Originally posted by: covert24
what is SSE5 supposed to accomplish? what type of instructions does this have in relation to SSE4?

It's basically "we didnt implement all of SSE4, so we will just tack on some of our own code that doesnt do much and call it SSE5".

In my eyes :thumbsdown:

Anand said it should be the most significant improvement since SSE2.

 

[CTho9305]

Originally posted by: pm
Doesn't Core 2 Duo achieve something similar to a 3 operand FMAC instruction by using macro-op fusion?

This is a serious question by the way. I am not any kind of microprocessor architect type person and don't pretend to be.

It may to some extent. As I understand it, MCW can only fuse certain kinds of operations though (e.g. compare + jump), and I'm not sure if the macro op fusion just saves slots in various queues and the reorder buffer or if it can actually chain operations reducing the overall latency (I don't think there's any savings available for integer ops, but for FP ops, you might be able to reduce the overhead of aligning and rounding between instructions).

Even if it can combine fadd and fmul or SSE equivalents at reduced latency, there's still another advantage the 3-operand instructions have: fetch bandwidth (and, I guess, I-cache usage). Keeping a fast SIMD backend full requires shoveling huge amounts of instruction data into the frontend of the machine, because a lot of newer instructions have longer opcodes (plus prefixes). As the average instruction size increases, combining instructions becomes a bigger win. In the case of the example here, mulps + addps + shufps + movaps= 8 bytes for the "kernel" in the second half, while fmaddps + permps = 6 bytes (ignoring prefixes, and assuming I'm counting correctly).

 

[pm]

Very helpful answer. Thanks, CTho9305.

 

[Acanthus]

Originally posted by: ObscureCaucasian

Originally posted by: Acanthus

Originally posted by: covert24
what is SSE5 supposed to accomplish? what type of instructions does this have in relation to SSE4?

It's basically "we didnt implement all of SSE4, so we will just tack on some of our own code that doesnt do much and call it SSE5".

In my eyes :thumbsdown:

Anand said it should be the most significant improvement since SSE2.

Time will tell, im just saying what it looks like to me.

 

[Khato]

Originally posted by: SickBeast

Originally posted by: adairusmc

Originally posted by: Mitch101


Its pretty clear that AMD should receive a large settlement from the lawsuit against Intel

:laugh:

What's so absurd about that? Intel is known to have strongarmed the chipset and motherboard partners to avoid building AMD parts. IMO AMD *should* be compensated for that. We can't have large corporations behaving in this way. They're already more powerful than any government on earth. :light:

Oh? Intel did that? Or is that just the typical conjecture that gets labeled as fact because you want it to be so?

Really though, this is little more than a 'me first' announcement. CPU development cycle is how long? 4 years? And remind me what one of the first things in the development stage would be, oh, maybe the instruction set? So you -know- Intel already has the real SSE5 instructions defined, they just wait until about a year to announce, if that.

 

[nyker96]

soon they'll be pushing SSE10 which is ...

 

[Fox5]

It'd be funny if Intel announced their own SSE5.
Since AMD isn't supporting all of SSE4, I'd say intel is more than in their own right to do so. AMD should have supported all of SSE4's instructions just for compatibility purposes, even if some took multiple cycles to execute and didn't give a speed advantage.

 

[Idontcare]

Originally posted by: Acanthus

Originally posted by: covert24
what is SSE5 supposed to accomplish? what type of instructions does this have in relation to SSE4?

It's basically "we didnt implement all of SSE4, so we will just tack on some of our own code that doesnt do much and call it SSE5".

In my eyes :thumbsdown:

Who cares what they do or don't do, what they call it or don't call it?

I don't care where performance improvements come from, nor do I care what they are called.

Are you so choosy that you won't buy processor XYZ because of who makes it or what the maker calls it even perchance it gives you more performance per dollar, per watt, per whatever?

I will never understand the premise in these threads that if innovation in one's product is not perceived to be from pristine virginal-like sources and aspirations then it is not worthy of being used to a customer's benefit.

I say bring on SSE5, bring on chips and salsa, bring on 10GHz single-core or 2GHz Octal-core, bring on whatever so long as it means more performance for my applications of interest.