Question AMD Phoenix/Zen 4 APU Speculation and Discussion

[maddie]

Do we know whether AMD plans to do SOIC packaging on its own like it does with substrate packaging? If not I expect it to cost more in any case just for the reason AMD can't move it in-house and directly profit of economy of scale. I haven't seen any news indicating the TF AMD packaging plant in Malaysia, the current or the upcoming one in next year, is capable of SOIC or not.

ASFAIK the SOIC bonding process takes place at TSMC, just like producing the chiplets. I can't see them allowing off site anytime soon. Critical tech for competing against other fabs.

If anything, as more TSMC customers begin using SOIC, the volumes will be greater than AMD alone can generate.

 

[moinmoin]

ASFAIK the SOIC bonding process takes place at TSMC, just like producing the chiplets. I can't see them allowing off site anytime soon. Critical tech for competing against other fabs.

If anything, as more TSMC customers begin using SOIC, the volumes will be greater than AMD alone can generate.

My point is when TSMC does it it will likely be a fixed fee, with economy of scale likely not being used to reduce the fee for the customers like AMD. Unlike with packaging done in-house where AMD directly profits from improvements and economy of scale.

 

[maddie]

My point is when TSMC does it it will likely be a fixed fee, with economy of scale likely not being used to reduce the fee for the customers like AMD. Unlike with packaging done in-house where AMD directly profits from improvements and economy of scale.

Don't you think TSMC passes some of the scaling benefit savings to their customers? It's a fee, but it can also change +/- depending on costs.

 

[tomatosummit]

Don't you think TSMC passes some of the scaling benefit savings to their customers? It's a fee, but it can also change +/- depending on costs.

It has potential to be a monopoly today. We know tsmc has been expanding their packaging facilities and 3d integration is likely a part of that. I doubt we'll find out how it's costed to customers today for a while. It might even be partially subsidised by the increased wafer costs of n7/n5 so customers stick with tsmc and are more inclined to stick with their new packaging technology.
This is probably why there's an industry push towards open chiplet interconnects so third parties can be involved in more packaging again and reintroduce some competition.

 

[moinmoin]

Don't you think TSMC passes some of the scaling benefit savings to their customers? It's a fee, but it can also change +/- depending on costs.

We were talking about whether SOIC could be cheaper than bog standard substrate packaging. Maybe it could, if AMD does SOIC itself as well. As is AMD does substrate packaging itself whereas SOIC is a service bought from TSMC. Even if the latter is the cheaper work of the two, as an external service it's very likely more expensive. As any company TSMC will want to have some profit margin there.

 

[MadRat]

With chiplets they only need TSMC for the finest, highest granular parts. At a certain point a third party should be able to build the substrate and add on the modular parts. Its on the designer to build flexibility into that further development, not TSMC.