Question AMD Phoenix/Zen 4 APU Speculation and Discussion

[uzzi38]

I can finally make this thread.

https://twitter.com/x/status/1519669375283957760

Phoenix is indeed RDNA3. My advice to everyone: treat the old APU rumours as being out of date.

 

[TESKATLIPOKA]

Err... I'm assuming that you meant 2x GFLOPS per CU/WGP there?

A single 256 ALU RDNA3 WGP would need to be running at 2 Ghz just to get 1 FP32 TFLOPS unless I missed something in the specs so far.

It doesn't matter If I wrote GFLOPs or TFLOPs, because It's still 2x more per CU/WGP than RDNA2. Unless you were talking about something else?

 

[moinmoin]

The Xilinx part coming in AMD chips is XDNA AIE, and Phoenix includes it.

Edit:

Odd slide, "Phoenix Point" instead Phoenix, and Strix Point with Zen 5 which would break with the yearly APU cadence unless the Zen 5 APU is officially launched first ahead of other Zen 5 chips (no chance imo).

 

[Asterox]

The Xilinx part coming in AMD chips is XDNA AIE, and Phoenix includes it.

Edit:

Odd slide, "Phoenix Point" instead Phoenix, and Strix Point with Zen 5 which would break with the yearly APU cadence unless the Zen 5 APU is officially launched first ahead of other Zen 5 chips (no chance imo).

It is AMD slide, but in general i didn't expect any Xilinix IP so quickly in AMD APU.

AMD Details Strategy to Drive Next Phase of Growth Across $300 Billion Market for High-Performance and Adaptive Computing Solutions

AMD unveils next-generation hardware and software roadmaps, expanded product portfolio addressing new markets, and strategies to accelerate data center...

www.globenewswire.com

"AMD XDNA, the foundational architecture IP from Xilinx that consists of key technologies including the FPGA fabric and AI Engine (AIE). The FPGA fabric combines an adaptive interconnect with FPGA logic and local memory, while the AIE provides a dataflow architecture optimized for high performance and energy efficient AI and signal processing applications. AMD plans to integrate AMD XDNA IP across multiple products in the future, starting with AMD Ryzen™ processors planned for 2023".

 

[moinmoin]

It is AMD slide, but in general i didn't expect any Xilinix IP so quickly in AMD APU.

Earlier this year Xillinx IP was announced to start appearing in AMD chips by 2023. This is the first concrete result. Epyc chips will get it as well. It appears talks about including Xillinx IP were happening even before the merger talks, and then everything came together.

 

[moinmoin]

AMD Details Strategy to Drive Next Phase of Growth Across $300 Billion Market for High-Performance and Adaptive Computing Solutions

Browse AMD’s company-wide and financial press releases.

ir.amd.com

“Phoenix Point” innovations include the AIE inference accelerator, image signal processor, advanced display for refresh and response, AMD chiplet architecture, and extreme power management.

So Phoenix Point will already be chiplet based. There is a chance that aside XDNA AIE Xillinx may also contribute to the signal processor, display and media engine.

AV & Entertainment

Solutions from AMD are built on a 20+ year history of servicing different facets of the AV & Entertainment industry – from timing controllers in modern TVs to optical engines in projectors, from real-time gaming to the brains inside premium drones, and from signal processing inside audio...

www.xilinx.com

 

[leoneazzurro]

https://twitter.com/x/status/1535064256126652417

Very interesting if it is not a typo. Well, it may be that the chiplet may refer to the AIE only, or something more extreme.

 

[ahimsa42]

AMD Phoenix Point 4nm APU With Zen 4 & RDNA 3 In 2023, Strix Point APUs With Zen 5 & RDNA 3+ In 2024 For Laptops

AMD will be launching its Phoenix Point 4nm APUs with Zen 4 & RDNA 3 in 2023, followed by Strix Point with Zen 5 & RDNA 3+ cores in 2024.

wccftech.com

does this remind anyone else of the south park episode with george rrr martin & the dragons?

 

[nicalandia]

The Xilinx part coming in AMD chips is XDNA AIE, and Phoenix includes it.

That's Xilinx AI Engine IP

Xilinx AI Engine Technology White Paper PDF

https://www.xilinx.com/content/dam/xilinx/support/documents/white_papers/wp506-ai-engine.pdf

 

[itsmydamnation]

The Xilinx part coming in AMD chips is XDNA AIE, and Phoenix includes it.

Edit:

Odd slide, "Phoenix Point" instead Phoenix, and Strix Point with Zen 5 which would break with the yearly APU cadence unless the Zen 5 APU is officially launched first ahead of other Zen 5 chips (no chance imo).

they did say both 4nm and 3nm Zen5 , could we see a 4nm Zen5 APU first?

 

[moinmoin]

That's Xilinx AI Engine IP

Xilinx AI Engine Technology White Paper PDF

https://www.xilinx.com/content/dam/xilinx/support/documents/white_papers/wp506-ai-engine.pdf

Indeed, and the new brand name as part of AMD now is AMD XDNA AIE, see e.g. (from slide 25 in Victor Peng's talk):

 

[tomatosummit]

Very interesting if it is not a typo. Well, it may be that the chiplet may refer to the AIE only, or something more extreme.

I'm hoping for some kind of memory chip. Something like the memory interface chiplet that's part of navi31/32 to get some actual memory bandwidth to phoenix. lpxDDR5 alone isn't going to cut it if it's really a gpu monster like rumoured.

 

[nicalandia]

I'm hoping for some kind of memory chip. Something like the memory interface chiplet that's part of navi31/32 to get some actual memory bandwidth to phoenix. lpxDDR5 alone isn't going to cut it if it's really a gpu monster like rumoured.

AI Engine is something entirely different from memory bandwidth, It will be placed on the IO as required by the SKU and it will serve as a feature set to compliment AMD stack.

AMD XDNA Diagram

 

[Glo.]

If its Chiplet based - the SoC has to have system cache.

Infinity Cache Chiplet?

I am more than surprised that it is indeed chiplet based.

 

[Kaluan]

I got you. Let me summarize it here.

Phoenix:
- Reiterated that Phoenix is designed to put pressure on the low-end GPU market
- 6 WGP for Phoenix iGPU
- >3 GHz for iGPU
- 2023 CES debut
- 8 Zen 4 cores w/ 16 MB L3 cache
- Doubled L2 cache, presumably no Infinity Cache
- How will the iGPU achieve its performance targets without Infinity Cache? Apparently, it will be due to high clocked memory (8500 MT/s) using a really good memory controller

View attachment 61248
View attachment 61249
View attachment 61250

Zen 5:
- Zen 5 and RDNA4 uses TSMC N4 (again, highly customized by AMD)

TSMC Updates:
- AMD intends to pay 6.5B to TSMC/GloFo for the rest of the year's chip capacity

Looks like N3(E?) will also play a role in Zen5, so the N4 rumors were off. I could go off about a "generic" N3 compute chiplet + N4 IOD, but we all already know Zen5 will be a big redesign (bigger than Zen1 -> Zen2 possibly), so it's useless to speculate much right now. Conventional Zen wisdom may not apply to Zen5 at all. Hell, from the AMD FD slides it looks like RDNA3 might use stacking, few people expected it.

Theres no way the OEMs will put 8500MT memory on their laptops just cause AMD designs for it. If AMD is designing it for that, I hope they have some partnered designs that actually come out with that. APUs are so memory limited at some point they will need infinity cache.

LPDDR5X is 7500-8533MTs, if 8533MTs is too exotic/expensive 10 months from now, maybe 7500MTs is a more realistic "compromise"?

AMD Phoenix RDNA3 iGPU could be as fast as the slowest GeForce RTX 3060 mobile GPU - VideoCardz.com

AMD Phoenix APU with mid-range discrete GPU performance Greymon55 claims that the upcoming integrated graphics into the AMD Phoenix APU, could show comparable performance to the most power-restricted version of the RTX 3060 mobile. AMD Ryzen 7000 series will officially include two mobile series...

videocardz.com

Far fetched maybe (2,5x improvement vs typical Radeon 680M iGPU performance), but I do see a scenario where this is very plausible.
One were you pit a 60W 3060M + whatever the CPU it's paired with uses in gaming benchmarks (85W total?) VERSUS top Phoenix Point SKU running at above it's rumored 35W TDP, or roughly the same ~85W TDP as the 60W+CPU 3060M system.
Radeon 680M already needs north of 30W for itself alone to hit and stay at it's rated 2,2/2,4GHz clocks. It's likely RDNA3 iGPUs will also need a somewhat generous power budget to hit and keep the reported 3GHz clocks in game.

 

[soresu]

Looks like N3(E?) will also play a role in Zen5, so the N4 rumors were off. I could go off about a "generic" N3 compute chiplet + N4 IOD, but we all already know Zen5 will be a big redesign (bigger than Zen1 -> Zen2 possibly), so it's useless to speculate much right now. Conventional Zen wisdom may not apply to Zen5 at all. Hell, from the AMD FD slides it looks like RDNA3 might use stacking, few people expected it.



LPDDR5X is 7500-8533MTs, if 8533MTs is too exotic/expensive 10 months from now, maybe 7500MTs is a more realistic "compromise"?

AMD Phoenix RDNA3 iGPU could be as fast as the slowest GeForce RTX 3060 mobile GPU - VideoCardz.com

AMD Phoenix APU with mid-range discrete GPU performance Greymon55 claims that the upcoming integrated graphics into the AMD Phoenix APU, could show comparable performance to the most power-restricted version of the RTX 3060 mobile. AMD Ryzen 7000 series will officially include two mobile series...

videocardz.com

Far fetched maybe (2,5x improvement vs typical Radeon 680M iGPU performance), but I do see a scenario where this is very plausible.
One were you pit a 60W 3060M + whatever the CPU it's paired with uses in gaming benchmarks (85W total?) VERSUS top Phoenix Point SKU running at above it's rumored 35W TDP, or roughly the same ~85W TDP as the 60W+CPU 3060M system.
Radeon 680M already needs north of 30W for itself alone to hit and stay at it's rated 2,2/2,4GHz clocks. It's likely RDNA3 iGPUs will also need a somewhat generous power budget to hit and keep the reported 3GHz clocks in game.

Odd that neither Zen4 Raphael nor Dragon Range was discussed at the FAD while they produly put forward codenames for 2024 Zen5 Granite Ridge and Strix Point don't you think?

 

[yuri69]

How will be the software for Phoenix's AIE written? Who will write the apps? What kind of mobile/APU-class apps need AIE?

It kinda sounds like dead silicon given AMD's APU market share.

 

[Mopetar]

How will be the software for Phoenix's AIE written? Who will write the apps? What kind of mobile/APU-class apps need AIE?

It kinda sounds like dead silicon given AMD's APU market share.

What do you mean how will it be written? The same way any other software is written. Unless AMD is only putting it there for internal use by the rest of the CPU components, they release an ISA that compilers can target and add tool support.

Mobile SoCs already have been including this kind of hardware for several generations. It's used for all kinds of things such as image processing.

The APUs aren't being used for other products unlike Zen chiplets so there would be no point in even including it if they didn't intend to enable it and for it to be useful for application developers. It's not going to be dead silicon.

 

[uzzi38]

How will be the software for Phoenix's AIE written? Who will write the apps? What kind of mobile/APU-class apps need AIE?

It kinda sounds like dead silicon given AMD's APU market share.

By the same metric I guess nobody will ever write software for Qualcomm phones, right? Because they only have 30% market share wrt mobile SoCs, just like how AMD only has about 22.5% laptop market share. And I guess Apple basically just doesn't exist at only 15%.

 

[uzzi38]

That's Xilinx AI Engine IP

Xilinx AI Engine Technology White Paper PDF

https://www.xilinx.com/content/dam/xilinx/support/documents/white_papers/wp506-ai-engine.pdf

The website actually has some more information on it not included in the PDF, like the actual output of each of the two types of AIE tile: https://www.xilinx.com/products/technology/ai-engine.html

 

[Mopetar]

What I'm most excited about isn't so much the AI blocks or even Phoenix, as good as it will probably be, but what AMD will do with APUs going forward. While talking about CDNA the had a slide that showed a unified HBM for for CPU/GPU on Instinct parts.

I hope that we see some of this make the hop to consumer space. HBM on an APU would be insane, and I think a unified SLC would also be what would really let consumer APUs punch above their weight.

 

[moinmoin]

I think XDNA AIE deserves its own thread for dedicated speculation and discussion so I started it here:

Discussion - AMD XDNA AIE and FPGA Speculation and Discussion

Next to Zen, RDNA and CDNA the Xilinx contributed XDNA is AMD's next major core IP joining. (Source: slide 3 Mark Papermaster presentation) It will first joining us with the Rembrandt sucessor Phoenix Point. (Source: slide 11 Saeid Moshkelani presentation) AI Engine (AIE) and FPGA are...

forums.anandtech.com

While talking about CDNA the had a slide that showed a unified HBM for for CPU/GPU on Instinct parts.

Though that's achieved by having Zen cores as part of the Instinct module.

 

[DisEnchantment]

What I'm most excited about isn't so much the AI blocks or even Phoenix, as good as it will probably be, but what AMD will do with APUs going forward. While talking about CDNA the had a slide that showed a unified HBM for for CPU/GPU on Instinct parts.

I hope that we see some of this make the hop to consumer space. HBM on an APU would be insane, and I think a unified SLC would also be what would really let consumer APUs punch above their weight.

Indeed, I am wondering what AMD really meant with that statement that Phoenix is using chiplet architecture.
Not sure if it is something they will do but cache chiplet will bring tangible improvements in graphics which can be perceived by users immediately.

If there is some infinity cache, with 12CUs @~2.5 GHz it would be beyond RX470 level in TF and considering the gen on gen gains that would be some capable GPU in a thin notebook.
They can remove that chiplet for business laptops.
Phoenix looks like its going to be a great chip, very well balanced.
The N4 should help bring that TDP back to 15W or less for many SKUs and improving sustained performance. Should greatly help x86 efficiency standing in mobile.

In the end the bean counters will decide probably.

 

[DrMrLordX]

How will be the software for Phoenix's AIE written?

I think it's up to AMD to make sure that their AI acceleration hardware (AIE or otherwise) is compliant with existing APIs/programming toolchains. If someone has an inference workload, they're going to target an API, not a specific logic block.

 

[LightningZ71]

Something tells me that, just like DirectX, there's going to be a "DirectAI" programming interface for all the different AI accelerators soon.

 

[soresu]

Something tells me that, just like DirectX, there's going to be a "DirectAI" programming interface for all the different AI accelerators soon.

It's called DirectML and it's been around for a while as a part of DX12.