From 800 MHz, it would take a 150% overclock to meet the common 2.0 GHz rumor. Lets suppose that the overclocking gave a 100% speed boost (quite a large overclock in my opinion) then that would put it at 1.6 GHz which is scary if AMD probably can't meet it given 4-6 more months.
umm.. if you don't want to be called a dumbass for responding like that, I would suggest you rethink things...
first of all, we haven't a CLUE how fast this thing will actually be, just talking about mhz here.
second, we don't know the actual POWER of the chip; ie, the amount of things that it can do per clock cycle (just look at what it was compared to: Itanium).
heck, we don't even know the amount of power this thing is sucking through that motherboard, the cooling it's using (most likely something fairly decent considering AMD still doesn't have any sort of proper heat spreader), the transistor count (should be below 80 million considering Parhelia can only hit around 220mhz with that many transistors at .15 micron) or even the die process it was manufactured on (most likely .13 seeing as T-breds are probably already being mass produced getting ready for their launch).
there is no way in hell you can tell anything from the 800mhz number other than what the guy said, which could be true (we all know AMD tries at least a little bit to keep things secret).
remember, AMD relies on XP numbers now, not mhz. performance, not marketing. I'm just wondering how sweet that onboard memory controller will be, as it nearly eliminates the whole FSB bandwidth (unless you have an 8 MB AGP card and some sort of sweet SCSI setup + Gigabit Ethernet) and allows the former northbridge to be placed differently (nearer to the AGP slot) while the CPU can move closer to the RAM, making latencies due to trace lengths shorter.
this is going to be one interesting architecture, you have to think a little bit different with it.. doesn't it reduce the pin count of the 'northbridge' (no 64 bit bus for the DDR SDRAM)? I think SiS might have had something going with their single chip solution, they just placed it on the wrong architecture! this way the devices connected to the southbridge don't have to go so far (through the northbridge AND the CPU) to get to the RAM.