Question AMD Laying off 4% of worldwide workforce to "focus more on AI"

[LightningZ71]

IPC not perf.

If that's the case, I stand corrected. That does leave open the possibility for larger CCD usage.

 

[inquiss]

If that's the case, I stand corrected. That does leave open the possibility for larger CCD usage.

And gains to come from elsewhere too - not just the core improvements. Gaming could improve via latency reduction, for example.

 

[OneEng2]

On the "leaked" slide that was circulated here a while back, they were showing an expected total performance uplift for Zen6 over Zen 5 of about 10% or so. I don't think going from 16 to 32 cores on desktop would give so little.

I just don't think we'll see server CCDs on normal AM5 processors. Aside from what a few of our more trusted posters have said in the past, there's no competitive need for server CCDs with full blown AVX512 implementations on desktop, especially where they will hit a brick wall with memory throughput.

Seems like pretty easy pickings for AMD to make a top tier desktop CPU having two 16 core CCD's for Zen 6. No guarantee at all they will choose to do so, but certainly a possibility.

And gains to come from elsewhere too - not just the core improvements. Gaming could improve via latency reduction, for example.

... and increased bandwidth memory support which would be especially needed should core counts double. Of course, X3D cache helps in many instances with main memory bandwidth limitations.... but not all.

 

[inquiss]

Seems like pretty easy pickings for AMD to make a top tier desktop CPU having two 16 core CCD's for Zen 6. No guarantee at all they will choose to do so, but certainly a possibility.

... and increased bandwidth memory support which would be especially needed should core counts double. Of course, X3D cache helps in many instances with main memory bandwidth limitations.... but not all.

Increased bandwidth support, agreed. I don't subscribe to either the need, or to the passing on the costs to regular consumers that don't need the channels, of increasing channel support on the mainstream platform though. Incredibly the size of the links should increase the amount of bandwidth through the IO die to the CCD, which single CCD SKUs could really do with. Wonder how they increase infinity fabric bandwidth for zen 6

 

[LightningZ71]

I suspect that the rumored divergence between client and server CCDs will be, in part, because both will have different links to the I/O die, in location, in type and general implementation. Going forward, they have diverging needs...