AMD Intends to Increase Cache Sizes.

[Gamer X]

X bit Labs

Advanced Micro Devices, the world?s second largest maker of microprocessors, has singed an agreement with Innovative Silicon Inc., a startup that has developed zero-capacitor memory (Z-RAM) technology that allows to increase processor caches by up to five times without increasing the size of the die.

?The dramatic increase in density offered by ISi?s Z-RAM embedded memory can enable much larger on-chip microprocessor cache memories resulting in improved performance and reduced I/O power consumption,? said Craig Sander, corporate vice president of technology development at AMD, EETimes web-site reports.

The Z-RAM technologi is capacitor-less, single transistor DRAM harnessing the floating body effect of Silicon on Insulator (SOI) devices. This technology is capable of achieving twice the memory density of existing embedded DRAM technology and five times that of SRAM, which is used for processor caches, yet requires no special materials or extra mask/process steps. The Z-RAM technology requires silicon-on-insulator process technology and thus will suit for AMD?s central processing units (CPUs).

?We?ve looked at data from Innovative Silicon and it looks very promising. We still need to assure ourselves that this will work in our own application. We need to see how it scales and we need to make our own test vehicles,? Mr. Sander is reported to have said. It is expected that AMD will test the technology at its 65nm and 90nm nodes located in its Fab 30 and Fab 36, Dresden, Germany.

Advanced Micro Devices traditionally has been behind Intel Corp., the world?s largest maker of microprocessors, when it comes to large on-die caches. Even now loads of microprocessors from AMD have less than 1MB of cache, whereas Intel Corp. supplies chips that integrate more than 4MB of cache to the desktop market. In server space AMD?s chips sport a little bit more than 2MB of cache, whereas Intel commercially ships processors with more than 8MB which significantly boosts performance in multi-threaded applications.

The new technology should allow AMD not only to increase the cache sizes of its processors, but also to offer a very significant performance advantage over competing solutions, as, depending on the application, AMD-based computers outperform Intel-based systems in a lot of cases.

It is unclear when AMD will be in position to use Z-RAM technology.

 

[pm]

From: http://www.us.design-reuse.com/news/news9538.html

Lausanne, Switzerland, Jan 24, 2005 --Innovative Silicon Inc. (ISi) has launched its Z-RAM?embedded memory technology for SoCs which doubles memory density when compared to existing embedded DRAM solutions. The Z-RAM (Zero Capacitor RAM) technology harnesses the Floating Body (FB) effect that occurs in Silicon-On-Insulator (SOI) devices, resulting in a cell structure that is based on a single transistor alone, rather than the combination of a transistor and a capacitor. Z-RAM memory designs have been taped out at 90nm and the technology is scalable to 22nm design rules. More, unlike other high density memory technologies, Z-RAM technology requires no extra mask steps, or exotic materials.
In SOI devices, the Floating Body or Body Charging effect which results in a charge developing in the FET device body has generally been considered as a parasitic effect. ISi has developed a mechanism to control and enhance this FB charge, which can then be used to store ?1? or ?0? binary states. Information is read by comparing the current in a selected cell to a reference, using a current sense amplifier.

This is pretty neat. That's a really interesting way to do it - I've long known about the hytersis effect of the body on SOI, I never considered that you could make a memory storage element out of it. Pretty cool stuff. I wonder how it handles low-voltages and soft-errors - especially the new SER quantum-like low-voltage problems that are cropping up at 45nm and 65nm. It's also my understanding that the effect gradually reduces in magnitude as you scale process... and fully-depleted SOI doesn't suffer (or "have", depending on your view of it) it at all. The industry seems to be pursuing fully-depleted... I guess this would be a reason not to.

 

[BrownTown]

im still not sure how it works, sounds like its not logic based, but then maybe not based on capacitors either. Anyways, what really matters is the latentcy, you could always put DRAM on a chip at an even higher density, but the latentcy is much worse then SRAM. The cache miss rate on modern processors is already pretty low, so increasing the latentcy of the cache can slow you down alot even if you have alot mroe cache. Kinda like the 500 and 600 series P4 where they doubled the cache, but also increased latentcy 17% and they pretty much just cancel each other out.

 

[pm]

In a nutshell, on a CMOS transistor on an SOI process (such as used by AMD and IBM, but not used by anyone else that I can think of... Intel, TI, TSMC, NEC, Samsung, etc), the delay of the transistor (how fast the transistor is) depends on the history of the signals that were applied previously to the terminals. So the transistor has a memory of previously applied values. Which, now that I write this, seems like it's obvious that this would make a possible memory storage element, but normally this "feature" is a major pain - because it's difficult to track the history of signals on a transistor using current CAD tools for, for example, determining the speed of the final design, you have to assume the worst case (so that your chip works no matter what).

So normally this "feature" is considered a liability, or at least something that designers wish could be an asset but which is too hard to utilize effectively and is thus ignored.

In more gory details, this exerpt from EETimes explains it pretty well:
( http://ww.eetimes.com/issue/bb/showArti...D%3D57300076+body+hysteresis+soi&hl=en )
In partially depleted MOS transistors ? the only kind used in production SOI today ? the body of the transistor is a small, electrically isolated piece of silicon trapped between the active portions of the transistor and the insulating layer underneath. If this body is allowed to float, it will take on a voltage determined by the capacitive coupling between it and the other portions of the transistor. But the voltage ? or, more properly, charge ? on this floating body can affect threshold voltage, and hence the drive current, of the transistor.

Ideally, the floating-body effect can deliver a formidable performance gain. Two circumstances arise from that gain, Soisic's Pelloie said. First, the voltage on the body influences the transistor's threshold voltage. "If you switch the gate of the transistor from off to on, then the body potential increases, which yields a decrease of the threshold voltage and then an increase of the drive current," he said. "The switch is then faster than in the bulk CMOS case, where the body is grounded."

The second effect is another mechanism for influencing the threshold voltage. "When you use stacked transistors in a gate, like NAND, NOR and any other combinational gate with multiple inputs, the body-to-source voltage of the transistors corresponds to a forward-bias condition, and the threshold voltage is lowered," Pelloie said. "For bulk CMOS or in a grounded-body situation, if the source has a high voltage value, for instance Vdd [the power supply voltage], the body source voltage then becomes - Vdd and the transistor body source junction is reverse-biased." That increases the threshold voltage and lowers the drive current. Analyzed at the circuit level, he said, these two SOI advantages are combined and globally yield a higher-speed operation.

But there is a catch to these threshold-voltage-lowering mechanisms, as Pelloie explained: "Since the body is floating, it follows the variation of the other terminals of the transistor. The body voltage never keeps the same value, as the transistors are, most of the time, switching in normal operation mode. This results in what we call the history effect: The propagation delay and some other features of the gates depend on the history of the signals applied to their terminals."



What using this technology gets you is a very small high-speed memory element for use in a cache. Current cache designs on microprocessors use 6 transistors (6T). Current memory designs (DDR DRAM) use 1 transistor and 1 capacitor. Clearly something that needs 6 transistors to make one memory element is going to be a lot bigger than one that uses 1 transistor and a capacitor, or using this Z-RAM stuff, 1 transistor alone. The problem with slapping a whole lot of DRAM onto a chip to make a cache that's way bigger than what we currently use, is that the method used to make DRAM chips is quite a bit different from that used to make microprocessors, so it increases cost to add "embedded DRAM" to a design.

 

[BrownTown]

it will be interesting to see how these new technologies that AMD is liscenscing will make their way into future chips. Anyways, if it does turn out to be what it prommises you can expect that Intel will use it as well. By the time it comes into use Intel will be on SOI technology, so they will be able to impliment it if their tech works similar to IBM/AMDs current SOI, but from what i hear Intel is using a new type of SOI on the 45nm node, so maybe it won't work...

 

[Neos]

I for one have always pulled for AMD - am using thier product now, and even way back to the 486 clones.

I do wonder if when AMD is the top dog will we still feel the same.

Regardless - this is good news for AMD - and for us.

 

[TuxDave]

Originally posted by: pm

What using this technology gets you is a very small high-speed memory element for use in a cache. Current cache designs on microprocessors use 6 transistors (6T). Current memory designs (DDR DRAM) use 1 transistor and 1 capacitor. Clearly something that needs 6 transistors to make one memory element is going to be a lot bigger than one that uses 1 transistor and a capacitor, or using this Z-RAM stuff, 1 transistor alone. The problem with slapping a whole lot of DRAM onto a chip to make a cache that's way bigger than what we currently use, is that the method used to make DRAM chips is quite a bit different from that used to make microprocessors, so it increases cost to add "embedded DRAM" to a design.

I thought 6T memories was an SRAM design where you had two access transtors and 2 inverters in positive feedback. I'm not sure how bad leakage is for it but I had the opinion that SRAMs did not need to be refreshed. If caches were to move from SRAMs to a DRAM style design with a cap or an SOI floating body, they would be forced to refresh?

 

[BrownTown]

yes, this technology requires you to refresh the memmory cells every so often.

 

[pm]

It should need to be refreshed just like DRAM. That said, nowadays leakage burns power in SRAM circuitry and so CMOS has static power just like DRAM (and Z-RAM).

 

[BrownTown]

But chache nowadays is a very low power part of the CPU, its the decoders and ALUs that get really hot. So either way, power/heat isn't gona be the main concern.