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AMD/IBM 65nm SiGe

K

KingofFah

Senior member
I was looking around and noticed that I missed this.

I checked DT and didn't see that they posted any articles or news about it. Anyway, good to see that they are finally getting somewhere with that; it was such a long time ago that they had mentioned it.
 
It was for this reason I expected Brisbane to show a significant reduction in TDP and an equal increase clock headroom. Perhaps future revisions will show the advantages of this new process.
AMD and IBM are also developing Immersion Lithography which should increase frequency headroom and reduce TDP. However, in light of the recent Brisbane reviews, I will be a little more conservative about my expectations of this process, due in 2008.
 
Well, I am fairly sure that Brisbane is not using the process described in that article. It is simply the die shrink.
 
Originally posted by: KingofFah
Well, I am fairly sure that Brisbane is not using the process described in that article. It is simply the die shrink.
Click to expand...

This is correct, if they were these chips should be clocking up higher then what Anand, Firingsquad and TechReport are showing.

To see the actual data:
http://www.realworldtech.com/page.cfm?ArticleID=RWT123005001504&p=7

My guess is they likely left out one or more of the 4 stressers for this revision.
 
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