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AMD Happy with their First Fusion Processor Design

ajaidevsingh

Senior member
Mar 7, 2008
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"A co-leader of Advanced Micro Devices? central engineering group said that the company was quite satisfied with its first so-called accelerated processing unit ? a chip that features both x86 processing core as well as graphics processing core ? code-named Llano.

?We are quite happy with what we are seeing so far and believe that ?Llano? is really going to demonstrate the power of AMD?s two strengths: x86 CPUs and GPUs. The current schedule is for 2011 introduction so it is still early, but because we are using an existing CPU core for the first product and not making big changes in the memory structure right away, we feel quite confident about where we are with Llano,? said Chekib Akrout, corporate vice president of central engineering at AMD."


http://www.xbitlabs.com/news/c..._Processor_Design.html


EDIT:- Forgot to add the key word is monolithic chip...
 

Martimus

Diamond Member
Apr 24, 2007
4,487
151
106
Why aren't they using an MCM design? It would seem that would make more sense, especially for their first run through. Going Monolithic with this is baffling to me.
 

Phynaz

Lifer
Mar 13, 2006
10,143
816
126
Originally posted by: ajaidevsingh
"A co-leader of Advanced Micro Devices? central engineering group said that the company was quite satisfied with its first so-called accelerated processing unit ? a chip that features both x86 processing core as well as graphics processing core ? code-named Llano.

?We are quite happy with what we are seeing so far and believe that ?Llano? is really going to demonstrate the power of AMD?s two strengths: x86 CPUs and GPUs. The current schedule is for 2011 introduction so it is still early, but because we are using an existing CPU core for the first product and not making big changes in the memory structure right away, we feel quite confident about where we are with Llano,? said Chekib Akrout, corporate vice president of central engineering at AMD."


http://www.xbitlabs.com/news/c..._Processor_Design.html


EDIT:- Forgot to add the key word is monolithic chip...


They expect a 2008 cpu to compete with Intel in 2011?

Fail.


 

Gikaseixas

Platinum Member
Jul 1, 2004
2,841
218
106
Originally posted by: Phynaz
Originally posted by: ajaidevsingh
"A co-leader of Advanced Micro Devices? central engineering group said that the company was quite satisfied with its first so-called accelerated processing unit ? a chip that features both x86 processing core as well as graphics processing core ? code-named Llano.

?We are quite happy with what we are seeing so far and believe that ?Llano? is really going to demonstrate the power of AMD?s two strengths: x86 CPUs and GPUs. The current schedule is for 2011 introduction so it is still early, but because we are using an existing CPU core for the first product and not making big changes in the memory structure right away, we feel quite confident about where we are with Llano,? said Chekib Akrout, corporate vice president of central engineering at AMD."


http://www.xbitlabs.com/news/c..._Processor_Design.html


EDIT:- Forgot to add the key word is monolithic chip...


They expect a 2008 cpu to compete with Intel in 2011?

Fail.
I think they're just experimenting to see how the cpu part communicates with the gpu one. It's way too early to make a final judgement IMO.
 

heyheybooboo

Diamond Member
Jun 29, 2007
6,289
0
0
The design engineering of the chip has not really been the issue. TSMC came on board the SOI ship in the Spring of 2008 so Anton may have been scooped by Theo (hard to imagine, eh?) on this one. Clearly a half-node SOI GPU is in the works - the only question is it 40nm (the original gpu core projection for Fusion with the 45nm Shanghai die), 40nm gpu on 32nm, or some mix of 32nm and this 'mysterious' 28nm node.

The 'entry' level is to have 2 cpu cores with a single gpu core.

BUT ... it's the SSE5 instruction set to utilize the parallel processing capability of the gpu core that is the problem.

AMD ran the new SSE5 instructions up the flagpole in August of 2007 and no one (except maybe SUN) saluted.
 

ilkhan

Golden Member
Jul 21, 2006
1,120
1
0
Originally posted by: Martimus
Why aren't they using an MCM design? It would seem that would make more sense, especially for their first run through. Going Monolithic with this is baffling to me.
AFAIK AMD doesn't have the MCM experience with CPUs that Intel does.
 

Idontcare

Elite Member
Oct 10, 1999
21,127
56
81
Originally posted by: ilkhan
Originally posted by: Martimus
Why aren't they using an MCM design? It would seem that would make more sense, especially for their first run through. Going Monolithic with this is baffling to me.
AFAIK AMD doesn't have the MCM experience with CPUs that Intel does.
Translation - AMD might not have the IP rights necessary to create a functionally competitive (performance-wise and cost-wise) MCM part.
 

Martimus

Diamond Member
Apr 24, 2007
4,487
151
106
Originally posted by: Idontcare
Originally posted by: ilkhan
Originally posted by: Martimus
Why aren't they using an MCM design? It would seem that would make more sense, especially for their first run through. Going Monolithic with this is baffling to me.
AFAIK AMD doesn't have the MCM experience with CPUs that Intel does.
Translation - AMD might not have the IP rights necessary to create a functionally competitive (performance-wise and cost-wise) MCM part.
That makes sense. Thanks.
 

heyheybooboo

Diamond Member
Jun 29, 2007
6,289
0
0
Originally posted by: Martimus
Originally posted by: Idontcare
Originally posted by: ilkhan
Originally posted by: Martimus
Why aren't they using an MCM design? It would seem that would make more sense, especially for their first run through. Going Monolithic with this is baffling to me.
AFAIK AMD doesn't have the MCM experience with CPUs that Intel does.
Translation - AMD might not have the IP rights necessary to create a functionally competitive (performance-wise and cost-wise) MCM part.
That makes sense. Thanks.
Maybe ... but AMD "Magny Cours" DCM uses a 'shared' 12Mb pool of L3 cache between the dual-die 12-cores (which utilize an HT link to communicate). Fairly significant difference in architecture than the Intel MCM.

AMD's biggest problem with DCM on the enterprise side may well be Randy "Forty Percent" Allen - :shocked:



 

DrMrLordX

Lifer
Apr 27, 2000
16,775
5,756
136
It's a failure for the enthusiast. What's their target market? What kind of machines will sport these CPUs? If they can drop this in netbooks (or smaller mobiles devices), set top boxes, pre-packaged HTPC rigs, gaming consoles, etc. then I see nothing wrong with the launch date. Power consumption and heat output will also be an issue.

Additionally, we're talking about a CPU that will, to an extent, offer the ability to function as an out-of-order, multi-purpose CPU and an in-order, FP-intensive vector processing unit. Depending on how much GPU power this brings to the table, if they make those stream processors readily available for future (or existing) programs to exploit, Llano or one of its descendants could wind up bringing a lot of power to the table. But, that's a lot of ifs, and expectations will be based on intended applications more than anything else.
 
Dec 30, 2004
12,560
2
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Originally posted by: VirtualLarry
Originally posted by: Soulkeeper
2011 = FAIL !
Agreed. Especially if still running only dual-core.
Two cores aught to be enough for anybody! Really!
No, really, I'm serious. Software can't get much bigger unless they simply start programming in "for (i=1,<100000,i++).
 

Idontcare

Elite Member
Oct 10, 1999
21,127
56
81
Originally posted by: heyheybooboo
Originally posted by: Martimus
Originally posted by: Idontcare
Originally posted by: ilkhan
Originally posted by: Martimus
Why aren't they using an MCM design? It would seem that would make more sense, especially for their first run through. Going Monolithic with this is baffling to me.
AFAIK AMD doesn't have the MCM experience with CPUs that Intel does.
Translation - AMD might not have the IP rights necessary to create a functionally competitive (performance-wise and cost-wise) MCM part.
That makes sense. Thanks.
Maybe ... but AMD "Magny Cours" DCM uses a 'shared' 12Mb pool of L3 cache between the dual-die 12-cores (which utilize an HT link to communicate). Fairly significant difference in architecture than the Intel MCM.

AMD's biggest problem with DCM on the enterprise side may well be Randy "Forty Percent" Allen - :shocked:
The bolded part - it would kinda have to be wouldn't it? In order to not infringe on Intel's IP.

Considering that Intel has been generating MCM related IP since at least the pentium pro days, there's bound to some serious restrictions on AMD's degrees of freedom when it comes to carving out their own IP space for functionally competitive MCM products.

Intel and AMD cross-license a good deal of architecture/ISA IP, but MCM technology lies more in the realm of manufacturing technology and I highly doubt any of it is cross-licensed. That would be like Intel cross-licensing HK/MG to AMD. Not going to happen.
 

Viditor

Diamond Member
Oct 25, 1999
3,290
0
0
Originally posted by: Martimus
Why aren't they using an MCM design? It would seem that would make more sense, especially for their first run through. Going Monolithic with this is baffling to me.
They will probably expand into MCM after the intro. Remember that Magny-Cours is a 12-core Opteron due Q1 2010 which is basically an MCM of Istanbul (6-core Opteron that AMD demonstrated last month).
AMD's concept for Fusion is to make it somewhat modular, but if they used MCM for each Fusion core, it seems to me that they would run into too many latency problems.
 

Viditor

Diamond Member
Oct 25, 1999
3,290
0
0
Originally posted by: Idontcare


Considering that Intel has been generating MCM related IP since at least the pentium pro days, there's bound to some serious restrictions on AMD's degrees of freedom when it comes to carving out their own IP space for functionally competitive MCM products.

Intel and AMD cross-license a good deal of architecture/ISA IP, but MCM technology lies more in the realm of manufacturing technology and I highly doubt any of it is cross-licensed. That would be like Intel cross-licensing HK/MG to AMD. Not going to happen.
I don't imagine that there is any IP restrictions...their cross-licensing extends through almost everything that they make. The only exception has been x86 (which is mentioned seperately)...though it is part of the same agreement.

Just as Intel was able to use x86-64, AMD should have no problem with MCM.

As to manufacturing not being part cross-license, the reason that neither company copies the other is that it would be just too damned expensive. Not for the licensing, but to actually copy the process in time for shipping...along with the testing and tweaking needed...couldn't happen IMHO.
I know this is your field IDC...can you imagine a company completely changing over their manufacturing tech within those time frames?
 

Idontcare

Elite Member
Oct 10, 1999
21,127
56
81
Originally posted by: Viditor
Originally posted by: Idontcare


Considering that Intel has been generating MCM related IP since at least the pentium pro days, there's bound to some serious restrictions on AMD's degrees of freedom when it comes to carving out their own IP space for functionally competitive MCM products.

Intel and AMD cross-license a good deal of architecture/ISA IP, but MCM technology lies more in the realm of manufacturing technology and I highly doubt any of it is cross-licensed. That would be like Intel cross-licensing HK/MG to AMD. Not going to happen.
I don't imagine that there is any IP restrictions...their cross-licensing extends through almost everything that they make. The only exception has been x86 (which is mentioned seperately)...though it is part of the same agreement.

Just as Intel was able to use x86-64, AMD should have no problem with MCM.

As to manufacturing not being part cross-license, the reason that neither company copies the other is that it would be just too damned expensive. Not for the licensing, but to actually copy the process in time for shipping...along with the testing and tweaking needed...couldn't happen IMHO.
I know this is your field IDC...can you imagine a company completely changing over their manufacturing tech within those time frames?
To my knowledge Intel and AMD do not cross-license IP outside of the cross-applicable ISA and architecture patents.

In manufacturing (which includes process technology like SOI and HK/MG, as well as packaging technology that includes sockets, MCM, etc) practically nothing is cross-licensed.

The reason for this is not because of the time-frame involved, it is a competitive advantage to "block out" technical approaches to solving a problem. Have you wondered why Intel uses pinless CPU's on LGA sockets while AMD continues to use pinned CPU's on their sockets? It's not because one simply hasn't bothered to make the transition to the other yet.

HK/MG is another example, there is a reason IBM/AMD have not debuted HK/MG yet and it is not because they can't do it but because they can't do it yet in a way that doesn't infringe on process technology IP. When we draft patents on process tech we cover what we use in practice and we also expand the claims section to include the entire process space over which the application can be utilized, this "blocks out" an IP space to prevent competition from using the same process but at 50C higher temp or 10 mTorr lower pressure, etc. It is an industry wide approach to IP and is basically the sole reason you see differentiation in the process technology fielded by any given IDM.

When you see more than one company jump onto what seems like the same process tech bandwagon, stressed channels for instance, it is usually a sign of a pending IP battle brewing. We all file our patents at nearly the same time but the patent office takes 12-24 months to award the patent. Once the patent is awarded then the lawyers go to work forcing the other near-identical process users to license and pay royalties. Its rarely a pretty process to behold but I have seen it in action first hand (albeit in our favor thankfully).

IBM/AMD have publicly stated they delayed the HK/MG introduction as they are pursuing a gate-first approach whereas Intel's approach is replacement-gate. IBM/AMD are doing this because they have no choice, being late to the party they already missed out on all the critical IP needed to effectively build replacement-gate HK/MG IC's. Likewise depending on how much of a lead time IBM has on Intel in the area of gate-first HK/MG, we may simply never see Intel migrate to the gate-first approach as they will be blocked by IP unless they sign a lucrative royalty license deal with IBM/AMD (not likely to happen).

Virtually all industries operate this way to my knowledge. Where standards exist the companies cross-license so no anti-competitive lawsuits get spawned (be it CPU's, memory, automobiles, airplanes, etc) but the method of implementing the standard (manufacturing) becomes the differentiating special sauce unless you outsource and go fabless/productionless (AMD, OCZ, etc).
 

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