Phynaz
Lifer
- Mar 13, 2006
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That one is even more uncalled for.
Why? He's pointing our that you are not a CPU designer.
Is he incorrect?
That one is even more uncalled for.
Why? He's pointing our that you are not a CPU designer.
Is he incorrect?
That one is even more uncalled for.
On top of that it is, ironically enough, just your uninformed opinion of me.
that is not the career I chose to pursue
So you apparently have some kind of mental model of what realistic designs would be possible today. And you are implying that Bulldozer has to fit in there somehow.
That is exactly what I am doing.
I think most of us around here respect you as a software engineer
But this is not the case in this thread. The line of reasoning that you took from a simple set of cache sizes to claiming that you know which caches would be able to infer a bunch of other characteristics, including expected latency, well, is simply wrong. There is no other way to put it.
Good, then Hardball was not incorrect.
Yes he is.
He claimed I was uninformed, which I'm not.
Okay, here's my claim.
You are not a CPU designer in trade or practice. By not not having the years of experience that others that post here have in the field, and you when argue with and constantly belittle them, you make yourself look foolish.
I not only studied programming in school, I did it assembly language 35 years ago. I HAD to know cpu architectures. But you don't see me claiming that I know as much as you about GPU programming just because I have some background in it.
And in your world a software engineer couldn't possibly have any knowledge outside of his own little turf, right? Certainly not yours!
I think you need to cool it a little here.
I don't "claim to know", I speculate. I didn't make any actual claims, I just gave a rough ballpark estimate of what I am expecting to come from Bulldozer.
You are trying to make it sound like I gave some exact performance figures... which I clearly didn't. Then you are trying to make it sound like I am pushing these alleged performance figures as absolute facts... which I clearly didn't.
I was just speculating. I don't see anything wrong with that, even if it is on what you feel to be 'your turf'. I certainly don't feel like you have the right to be so condescending towards me.
I was only pointing out the line of reasoning that you used regarding caches in this thread, and nothing more.
I agree though, our tone got away from cordial pretty quickly, for that I do take responsibility, I shouldn't have come on so strong and caustic in this thread. We should cool it down a bit, nothing personal at all, really.
Trying to figure out cache balance without knowing about the rest of the architecture is a pretty difficult task. I am guessing that when both products are in the market you'll be able to better asses the answer.
If I'm not mistaken Deneb gained on average 5% more performance because of the larger L3. Though it still seems like AMD is behind Intel in terms of their caching/memory subsystem. A higher (3GHz) clocked NB/L3 alone would have added another ~5% extra performance to Deneb. I'm hoping after all the time spent designing BD, and from the lessons learned from K10/K10.5, that AMD can finally produce a CPU that can rival the cache speed/bandwidth/latency characteristics of Intel processors.
My guess is that the biggest surprise we will get with BD is how highly it will clock (+4GHz stock, ~5GHz Air OC).
This era is very much no longer a one-size-fits-all market. Bobcat, Llano, Bulldozer all speak to this reality. We shouldn't really be looking towards bulldozer as some kind of uber cpu that was designed with aspirations to conquer all markets and put a chicken in every pot along the way.
Do we really have to argue something about we know so little of? Different companies, more so different architectures use cache differently. For example, this arch would appear to give each core 2MB of L2 cache. Thats massive. 8x more than Intel's L2 per full core, and 4x more than module/core. That alone should tell us they are going about this problem differently. The only person that knows anything here is pretty much JF, who cant quite disclose much more info yet. So no need for all the name calling and ignorance.
It's very likely that AMD will compete with SB by releasing higher clocked BD at reasonable prices. One handicap that SandyBridge will have is that every CPU will have an IGP with it, unnecessarily increasing die size (cost), when enthusiasts will use a discrete Graphics card anyways.
How about this instead:
- Bulldozer is not Barcelona
- Sandy Bridge is not NetBurst
Let's all agree on this and move forward. If you've been in in the indsutry long enough then you should know that compaines learn from the past. Both companies learn.
99% of the details of BD architecture is never going to be released to the public.
To everyone saying that we know "very little" with regard's to Bulldozer's cache setup, I have a question to ask you (one which I already know the answer to, but will ask anyways).
When Bulldozer comes out, and if it happens to be the case that Bulldozer's cache setup (and practical function and performance) is extremely similar to Barcelona in terms of associativity, look-ups, etc then what will you people respond with? What will you say? That you were wrong to defend Bulldozer? That you're disappointed AMD did not significantly change the cache systems?
Or will many of you remain silent on the subject?
Based on my experiences over the years on tech forums, I'm guessing many of you will simply remain silent.
Ha yes, Brazos is so bad it actually is faster multithreaded than the fastest Atom available, much faster single threaded then the fastest atom available, better graphics than an additional chip atom requires to do anything graphical wise and has a lower idle power consumption than those parts... What a fail!!!My guess is that you and others will be wrong and Bulldozer will not match AMD's hype.
Brazos performance is already underwhelming compared to the AMD hype.
I would be shocked if Bulldozer debuts at 4Ghz stock clock speeds.
Bobcat from initial benchmarks already seems disappointing, especially given that it's a product debuting years after Atom. Llano will lose to Sandy Bridge in CPU performance, and Bulldozer is likely to lose to Sandy Bridge/Ivy Bridge in per-core performance.
With Bobcat and Llano specifically, AMD is gambling that consumers don't need (or want) more CPU performance, but they they need/want more GPU performance.
AMD's gamble could be a mistake, and their products may end up being answers to questions that nobody asked.
That is a very daring post you've made there, full of assumptions.
So you're basically claiming that nobody here except JF knows anything, and you are implying that nobody else here is an insider for either company other than JF?
Furthermore, for those of us that are non-insiders, you are claiming that we know very little about the topic at hand, which is IMHO an insulting statement. Many non-insiders here have studied and/or have specialized in CPU architectures for years, if not decades. I think some of these members would also find your statements insulting.
Some of us have seen the Bulldozer slides, and the architecture details and architecture breakdown. Based on current and past CPU architectures, some members here can make accurate guesses on what Bulldozer's potential performance will be, even if they are non-insiders.
Since JF admits to working for AMD, there is a conflict of interest as he may post certain things that are more hype than fact, or more ambiguous than concrete.
Let me guess, did you also believe everything JF said or implied regarding Bobcat?
... Except that BD won't compete directly with the regular Sandy Bridge products. BD will compete with the enthusiast/server Sandy Bridge E products that will not have an IGP.
Sandy Bridge is not Nehalem either. Sandy Bridge has quite a few significant changes compared to Nehalem in-fact. Sandy Bridge even has a different L3 architecture with the "ring bus" setup.
Keeping all of this in mind however, Sandy Bridge's L2 and L3 caches are expected to perform and behave similarly to Nehalem in practice. Performance will likely be improved, but they will function in a similar manner to Nehalem.
Correlation does not always equal causation. Just because Bulldozer is a new architecture and a significant change from Barcelona does not mean the cache system will function in a significantly different manner.
Huh? Of course they will be, especially by the time Bulldozer launches. By Bulldozer's launch, we WILL publicly have a great amount of detail about Bulldozer's architecture.
Since JF admits to working for AMD, there is a conflict of interest as he may post certain things that are more hype than fact, or more ambiguous than concrete.
Let me guess, did you also believe everything JF said or implied regarding Bobcat?
To everyone saying that we know "very little" with regard's to Bulldozer's cache setup, I have a question to ask you (one which I already know the answer to, but will ask anyways).
When Bulldozer comes out, and if it happens to be the case that Bulldozer's cache setup (and practical function and performance) is extremely similar to Barcelona in terms of associativity, look-ups, etc then what will you people respond with? What will you say? That you were wrong to defend Bulldozer? That you're disappointed AMD did not significantly change the cache systems?
Or will many of you remain silent on the subject?
Based on my experiences over the years on tech forums, I'm guessing many of you will simply remain silent.
Is it really though? Cache balance is well ... cache balance. Unless AMD has a totally new cache structure or heirarchy that they have so far kept hidden with regards to Bulldozer, I don't see why this is a "pretty difficult" task.
Cache balance, or more specifically cache ratio is a very straightforward topic. Bulldozer's architecture as a whole is not being discussed specifically, but mainly its cache ratio.
My guess is that you and others will be wrong and Bulldozer will not match AMD's hype.
Brazos performance is already underwhelming compared to the AMD hype.
I would be shocked if Bulldozer debuts at 4Ghz stock clock speeds.
That's assuming each AMD product is exemplary and fits a clearly-defined niche where there is a big-enough demand.
Bobcat from initial benchmarks already seems disappointing, especially given that it's a product debuting years after Atom. Llano will lose to Sandy Bridge in CPU performance, and Bulldozer is likely to lose to Sandy Bridge/Ivy Bridge in per-core performance.
With Bobcat and Llano specifically, AMD is gambling that consumers don't need (or want) more CPU performance, but they they need/want more GPU performance.
AMD's gamble could be a mistake, and their products may end up being answers to questions that nobody asked.
That is a very daring post you've made there, full of assumptions.
So you're basically claiming that nobody here except JF knows anything, and you are implying that nobody else here is an insider for either company other than JF?
Furthermore, for those of us that are non-insiders, you are claiming that we know very little about the topic at hand, which is IMHO an insulting statement. Many non-insiders here have studied and/or have specialized in CPU architectures for years, if not decades. I think some of these members would also find your statements insulting.
Some of us have seen the Bulldozer slides, and the architecture details and architecture breakdown. Based on current and past CPU architectures, some members here can make accurate guesses on what Bulldozer's potential performance will be, even if they are non-insiders.
Since JF admits to working for AMD, there is a conflict of interest as he may post certain things that are more hype than fact, or more ambiguous than concrete.
Let me guess, did you also believe everything JF said or implied regarding Bobcat?
... Except that BD won't compete directly with the regular Sandy Bridge products. BD will compete with the enthusiast/server Sandy Bridge E products that will not have an IGP.
Sandy Bridge is not Nehalem either. Sandy Bridge has quite a few significant changes compared to Nehalem in-fact. Sandy Bridge even has a different L3 architecture with the "ring bus" setup.
Keeping all of this in mind however, Sandy Bridge's L2 and L3 caches are expected to perform and behave similarly to Nehalem in practice. Performance will likely be improved, but they will function in a similar manner to Nehalem.
Correlation does not always equal causation. Just because Bulldozer is a new architecture and a significant change from Barcelona does not mean the cache system will function in a significantly different manner.
Huh? Of course they will be, especially by the time Bulldozer launches. By Bulldozer's launch, we WILL publicly have a great amount of detail about Bulldozer's architecture.
I say this with all due respect, no intent to offend, but your post absolutely communicates a message that you do not work in a professional capacity in any industry let alone in the semiconductor industry.
Is this correct?
I say this because you seemingly missed just about every point of every post you quoted as you attempted to contradict or disprove them piecemeal wise.
Take Phynaz's post for example...you obviously don't understand what all goes into developing a cpu's architecture and ISA if you don't get the truth behind Phynaz's statement that 99% of all that secret sauce (the details) will never be made public...you appear to be under the impression that the marketing details that are made public in the likes of Anandtech reviews and so on represent THE DETAILS of the architecture...this misperception on your part speaks volumes to which I am addressing.
In a technical sub-forum like this one there is a time to step up and interject your opinion and then there are times when it is best to sit back and absorb some of the info being presented to you.
It is my opinion that you are not absorbing the salient points of the information contained in this thread. Do with that what you will, discard it as misguided unsolicited advice or contemplate it as the constructive feedback it was intended to deliver.
correct. Everything we know says s2011 will NOT have on-chip GPUs, but all s1155 chips WILL have on-die GPUs.
This is something that I have mentioned a few times already. For those who aren't microarchitecture people, they go into discussions armed only with knowledge of marketing slides / powerpoint presentations, and feel justified brawling in discussions that have become very technical, without even bothering to build up a good foundation of knowledge regarding the topic, such as by going through an entire computer organization book to get an understanding of CPU microarchitecture. It can be quite annoying, but expected in such a public forum.if you don't get the truth behind Phynaz's statement that 99% of all that secret sauce (the details) will never be made public...you appear to be under the impression that the marketing details that are made public in the likes of Anandtech reviews and so on represent THE DETAILS of the architecture
For those who aren't microarchitecture people, they go into discussions armed only with knowledge of marketing slides / powerpoint presentations, and feel justified brawling in discussions that have become very technical, without even bothering to build up a good foundation of knowledge regarding the topic, such as by going through an entire computer organization book to get an understanding of CPU microarchitecture.
Even at launch, or well after launch, the real details of the architecture don't get published in its entirety. You do get block diagrams + a few paragraphs of write-ups that are simplified, which are just marketing material + commentary of reviewers such as Anand. That's it. If you want to know the real details of the architecture, then you would be dependent on the manuals/software optimization guides published by AMD and Intel, and both aren't exactly very heavy on their documentation. Sometimes, it is even found that the documentation is not entirely accurate as revealed by testing.Huh? Of course they will be, especially by the time Bulldozer launches. By Bulldozer's launch, we WILL publicly have a great amount of detail about Bulldozer's architecture.
Even at launch, or well after launch, the real details of the architecture don't get published in its entirety. You do get block diagrams + a few paragraphs of write-ups that are simplified, which are just marketing material + commentary of reviewers such as Anand. That's it. If you want to know the real details of the architecture, then you would be dependent on the manuals/software optimization guides published by AMD and Intel, and both aren't exactly very heavy on their documentation. Sometimes, it is even found that the documentation is not entirely accurate as revealed by testing.
For example, are you aware that even now, there has been little information published about the branch prediction of the i7? Same goes for Deneb's L2 and L3 latency, all info about it are unofficial. AMD's optimization guide is also inaccurate in their branch predictor's misdirection penalty, by about 10-20%.
There are a lot of other examples that can be made, but the point should be clear - if we are to talk about microarchitecture on a level beyond that of marketing slides / powerpoint presentations and block diagrams, most of the information is kept under water like an iceberg.
For once, I do agree with your sentiments completely. I would personally prefer if such detailed information were not kept in secret.Its a stupid practice.
