Originally posted by: Phynaz
Originally posted by: Viditor
Originally posted by: Phynaz
Originally posted by: Viditor
I really don't understand some of the comments here...
Both Intel and AMD have done exactly the same thing with every single line!
Intel sold a lot of Pentium Ds as Celerons, AMD sold lots of Opterons with half of the cache disabled, etc...
Nothing has been said about the TriAthlon's availability or how many are being produced...
If only 10% have 1 defective core, then doesn't it make sense to sell them? That would represent close to a 90% yield at launch, which is insanely high...
Here we go again...
Yes, 90% yield is so insanely high as to be impossible.
AMD has stated
here defect densities below 0.5/cm2 range.
We know the die size, we know the process node, we know the wafer size, we know defect density, and we we know parametric yield is very low.
You now have everything you need to know to calculate the probe yield AMD is getting. I'll leave it to you to do the math. I suggest you use the Murphy yield model as it provides results closer to actual yields for large dies. Feel free to use the Seeds or Poisson models if you would like.
I think you're going to be surprised!
What the HELL are you talking about? That's the most insane thing I've ever seen!
1. What's a "probe" yield?
2. You can't calculate from die size, only from die dimensions (plus spacer and margin)
3. NOBODY has the defect density but AMD (saying it's below .5 cm2 is a very wide range still)
4. I have no idea what the other gibberish you spouting is, but why wouldn't I use one of the bucketloads of software packages that calculate it FOR me? (obviously it's gibberrish as you aren't even mentioning the right parameters...)
Edit...BTW, what does the process node have to do with anything in yield calculation?
Most people would Google the terms they don't understand rather than attacking the poster, or at least ask politly for an explanation.
Now, ignoring the attacks, you did ask two questions that I would be happy to explain to you, number 1, and your BTW. If you would like an explanation of points 2-4 please say so. But as I said in another thread, I'm not going to argue with you, because that's lame and boring.
1. Probe yield is the percentage of good chips found when the wafer is probed for defects. Modern fabrication methods use optical probing techniques to "look" for chip defects before they are sent to packaging.
For the answer to your BTW, yield and process size go hand in hand, along with probing. Assuming a 65nm process node, the maximum allowable physical defect size will be ~13 nm.
If you wish to spend a couple of hours educating yourself on yield management, there are many good papers available online for free. Even the Smithsonian archives contains papers on it.
Cheers!