AMD Confirms Three Core Phenom

[Phynaz]

PC Week news bit.

 

[tofumonster]

"The chips will actually be a four-core Phenom with one core disabled, according to AMD representatives."

I think that's a tad silly...but i'm not CPU junky. Its probably one of those "four cores is too many (and expensive for that matter) and two is too few, so i'll go with three" kind of situations (for the buyers anyways)

 

[Phynaz]

This raises the question - are dual core Barcelonas and Phenoms really quads with two defective cores?

 

[Ika]

It's probably not a good thing that AMD has so many defective cores that they can make a new line with them.

 

[Xcobra]

wow...AMD is REALLY desperate...

 

[Cookie Monster]

They are being desperate, or fighting to the best of their abilities. Why waste the defective X4 phenoms, when you can repackage them as X3? Im also sure the dual core X2s are native, as well as X4s being native meaning the X2/X4s use different chips unlike wolfdale/yorksfield combination.

This would be interesting seeing a tri core go up against dual/quad core solutions. Im intrigued by what kind of performance these tri cores can produce.

But this does seem to indicate yields not being terribly great.

 

[JackPack]

Originally posted by: Phynaz
This raises the question - are dual core Barcelonas and Phenoms really quads with two defective cores?

Probably. If dual-core Phenom was a different piece of silicon, AMD would have likely removed the L3, or at least reduced it.

 

[Cookie Monster]

Is that really true? is that why the die size of even the X2s (X4s with 2 cores disabled) are supposedly much more larger than the core2s?

 

[JackPack]

Originally posted by: Cookie Monster
Is that really true? is that why the die size of even the X2s (X4s with 2 cores disabled) are supposedly much more larger than the core2s?

I'm not aware of any die size estimates for Phenom X2. The official data only reveals that it has the same cache size and structure as X4/Barcelona.

 

[coldpower27]

Probably it will be a situation similar to the situation we had before.

Phenom x4 = Good Agena cores.
Phenom x3 = 1 Disabled Core Agena Core.
Phenom x2 = Combination of both a Native Kuma and Disabled Agenas

Phenom x3 requires disabled Agena's regardless of whether the core is fully working or not.

Phenom x2 will probably be native from the start and you won't see disabled Agena ones till AMD's has a built a decent stock on them.

 

[Cookie Monster]

Now that makes sense. Its a win-win situation for AMD this is the case. They can not only provide quad/dual core, but tri core as well. Id say that the performance/watt ratio of the tri core will be somewhere between a quad and dual which should give AMD some edge in the coming war with intel to come in the desktop market.

 

[darkfalz]

Yields must be awful and inconsistent, and AMD are trying to pinch every penny (they need to, they are going bankrupt). This indicates overclockability of Phenom will be almost nothing. The pathetic spin on defective CPUs is sad too, "Wow! Tri-Core exclusive to AMD!"

 

[Viditor]

I really don't understand some of the comments here...
Both Intel and AMD have done exactly the same thing with every single line!
Intel sold a lot of Pentium Ds as Celerons, AMD sold lots of Opterons with half of the cache disabled, etc...

Nothing has been said about the TriAthlon's availability or how many are being produced...
If only 10% have 1 defective core, then doesn't it make sense to sell them? That would represent close to a 90% yield at launch, which is insanely high...

 

[Phynaz]

Originally posted by: Viditor
I really don't understand some of the comments here...
Both Intel and AMD have done exactly the same thing with every single line!
Intel sold a lot of Pentium Ds as Celerons, AMD sold lots of Opterons with half of the cache disabled, etc...

Nothing has been said about the TriAthlon's availability or how many are being produced...
If only 10% have 1 defective core, then doesn't it make sense to sell them? That would represent close to a 90% yield at launch, which is insanely high...

Here we go again...

Yes, 90% yield is so insanely high as to be impossible.
AMD has stated here defect densities below 0.5/cm2 range.

We know the die size, we know the process node, we know the wafer size, we know defect density, and we we know parametric yield is very low.

You now have everything you need to know to calculate the probe yield AMD is getting. I'll leave it to you to do the math. I suggest you use the Murphy yield model as it provides results closer to actual yields for large dies. Feel free to use the Seeds or Poisson models if you would like.

I think you're going to be surprised!

 

[The-Noid]

AMD has done this forever, I had quite a few single core athlons that had a core disabled from a dual core. This is just good business.

 

[nonameo]

I imagine a CPU like this would make a good value for supreme commander.

 

[The-Noid]

You bring up a very good point. Most games are going to be trithreaded for sometime to come. Fully multi-threaded games may not come for some time.

 

[Viditor]

Originally posted by: Phynaz

Originally posted by: Viditor
I really don't understand some of the comments here...
Both Intel and AMD have done exactly the same thing with every single line!
Intel sold a lot of Pentium Ds as Celerons, AMD sold lots of Opterons with half of the cache disabled, etc...

Nothing has been said about the TriAthlon's availability or how many are being produced...
If only 10% have 1 defective core, then doesn't it make sense to sell them? That would represent close to a 90% yield at launch, which is insanely high...

Here we go again...

Yes, 90% yield is so insanely high as to be impossible.
AMD has stated here defect densities below 0.5/cm2 range.

We know the die size, we know the process node, we know the wafer size, we know defect density, and we we know parametric yield is very low.

You now have everything you need to know to calculate the probe yield AMD is getting. I'll leave it to you to do the math. I suggest you use the Murphy yield model as it provides results closer to actual yields for large dies. Feel free to use the Seeds or Poisson models if you would like.

I think you're going to be surprised!

What the HELL are you talking about? That's the most insane thing I've ever seen!

1. What's a "probe" yield?
2. You can't calculate from die size, only from die dimensions (plus spacer and margin)
3. NOBODY has the defect density but AMD (saying it's below .5 cm2 is a very wide range still)
4. I have no idea what the other gibberish you spouting is, but why wouldn't I use one of the bucketloads of software packages that calculate it FOR me? (obviously it's gibberrish as you aren't even mentioning the right parameters...)

Edit...BTW, what does the process node have to do with anything in yield calculation?

 

[Ghouler]

I think this is great idea to boost AMD sales.

Many people do not get "quad". They get "bi-" or "dual-" and they get "three" but "Quad" sounds to many like that name of a river in the north Morocco ...
(i.e.: who cares?!)
Also, people who are not that into CPUs would often buy second-best because they would expect better value from "the second-best" then from "the best". As long as Intel does not offer 3 core CPUs, second best place is taken. This might not be exactly technically right and I admit to simplify things but that's what you do when you buy something that you are not exactly able or willing to research in full, which happens a lot.

 

[SerpentRoyal]

1. Marketing gimmick.
2. Savaging dud quads.

What are you gonna do with dud quads, those with one or two bad core? Sell them as DUAL or TRIPLE core chips. Smart strategy to improve profit margin.

 

[SlowSpyder]

Originally posted by: Xcobra
wow...AMD is REALLY desperate...

I don't know about it being a desperate move... sounds like a smart move. Better then just throwing away a quad core processor because one core is bad. Also, they're the only one selling this, Intel does not have a tri-core. If they price it right, it'll find a place in the market with zero competition.

 

[Creig]

This is no different than when ATI or Nvidia took GPUs with defective pipelines, disabled them in the BIOS and sold them as lower-performing units. It's simply a way to maximize profits by using cores that would have otherwise been slated for scrap.

 

[Phynaz]

Originally posted by: Viditor

Originally posted by: Phynaz

Originally posted by: Viditor
I really don't understand some of the comments here...
Both Intel and AMD have done exactly the same thing with every single line!
Intel sold a lot of Pentium Ds as Celerons, AMD sold lots of Opterons with half of the cache disabled, etc...

Nothing has been said about the TriAthlon's availability or how many are being produced...
If only 10% have 1 defective core, then doesn't it make sense to sell them? That would represent close to a 90% yield at launch, which is insanely high...

Here we go again...

Yes, 90% yield is so insanely high as to be impossible.
AMD has stated here defect densities below 0.5/cm2 range.

We know the die size, we know the process node, we know the wafer size, we know defect density, and we we know parametric yield is very low.

You now have everything you need to know to calculate the probe yield AMD is getting. I'll leave it to you to do the math. I suggest you use the Murphy yield model as it provides results closer to actual yields for large dies. Feel free to use the Seeds or Poisson models if you would like.

I think you're going to be surprised!

What the HELL are you talking about? That's the most insane thing I've ever seen!

1. What's a "probe" yield?
2. You can't calculate from die size, only from die dimensions (plus spacer and margin)
3. NOBODY has the defect density but AMD (saying it's below .5 cm2 is a very wide range still)
4. I have no idea what the other gibberish you spouting is, but why wouldn't I use one of the bucketloads of software packages that calculate it FOR me? (obviously it's gibberrish as you aren't even mentioning the right parameters...)

Edit...BTW, what does the process node have to do with anything in yield calculation?

Most people would Google the terms they don't understand rather than attacking the poster, or at least ask politly for an explanation.

Now, ignoring the attacks, you did ask two questions that I would be happy to explain to you, number 1, and your BTW. If you would like an explanation of points 2-4 please say so. But as I said in another thread, I'm not going to argue with you, because that's lame and boring.

1. Probe yield is the percentage of good chips found when the wafer is probed for defects. Modern fabrication methods use optical probing techniques to "look" for chip defects before they are sent to packaging.

For the answer to your BTW, yield and process size go hand in hand, along with probing. Assuming a 65nm process node, the maximum allowable physical defect size will be ~13 nm.

If you wish to spend a couple of hours educating yourself on yield management, there are many good papers available online for free. Even the Smithsonian archives contains papers on it.

Cheers!

 

[Phynaz]

Paul Otellini on triple core at IDF:

"We see a distinctive advantage in having all the cores on one die work."

Ouch, that's gonna leave a mark!

 

[soonerproud]

Originally posted by: Phynaz
Paul Otellini on triple core at IDF:

"We see a distinctive advantage in having all the cores on one die work."

Ouch, that's gonna leave a mark!

Of course, that is assuming that the tri-core processor from AMD is simply a Quad with a disabled bad core. For all we know, they may have had a separate tri-core in the works for some time now. As secretive as AMD has been lately, this would not surprise me one bit.