>So in a sense this new Athlon64 is like going from a k6 to the K7? Slot-A Athlon, T-Bird, Pally, T-Bred, Barton.
So it seems to me. The K7 was an elaboration of the K6. A massive elaboration. With the K7, AMD decided to do a chip that was a big enough leap that Intel couldn't just up the timetable on their next generation 6 months and quickly leave AMD again as a second tier chip maker. I think people have said that AMD designs along these lines began with one of the K5's. There were at least 2 K5s that were totally different except for the name. The one that was designed by Nexgen, after AMD bought them, is the one that started this line.
People forget that Nexgen, before Intel, used a RISC processor to execute x86 instructions translated on the fly, in hardware, to behind-the-scenes RISC instructions, although it was not 100% x86 compatible. AMDs 100% x86 compatible K6 continued this. The K6 was designed to compete with Intel's Pentium, which was not RISC based. Intel didn't take long to get out the PII line, starting with the astronomically priced, oddball Pentium Pro and some stupendously expensive PII cartridge kludges, eventually progressing to a single chip socketed design. The PII dropped the K6 to second tier status a little too quickly. The K7 was a big enough stretch to keep AMD neck-and-neck with Intel for a long time. It was unnecessary for AMD to switch course like Intel did from the Pentium to the RISC based PII. The very high price of the PIIs worked out to AMDs advantage. It meant that AMD could make money even as expensive a stretch the K7 was for AMD. I'm sure AMD is looking forward to Intels K8 killer when it appears. By then the K8 process bugs should be worked out and AMD will be able to charge similar phenominal prices for the top speed K8s that will parallel Intel's killer.
>Are we going to see a progression with core modifications as we did the K7?
That's the way it alway is, isn't it? There were some pretty significant K7 performance redesigns at the Thunderbird and XP points. It hasn't been all die-shrinks to get the K7 up to 2000MHz. I forget where the first K7, slot A's started. 500MHz? It would be reasonable to expect the K8 engineers to have designed it for a similar run-up. 8000MHz? I don't think AMD will need a process shrink to get the K8 way above 2200MHz. Somewhere along the way to 8000MHz, IBM and AMD have something in the works, judging by the annoucements. It is interesting that both strained-silicon, now being exploited by Intel, and SOI, now being exploited by AMD, are both developments that came out of IBM. Actually, it seems like all developments somehow lead back to IBM.
One thing I found about from reading some Intel pdfs, is that the first silicon always has a lot of errors. Before they think about silicon, they create virtual chips as software that runs on vast banks of computers. (I'd like to see Intel's computer room. The one at Nvidia is quite impressive.) Unfortunately the software versions run too slowly to test thoroughly. It may take weeks or months to get to a DOS prompt. Only when it goes to silicon do they get to check it completely. They just revise as small a section as possible for the first retail product, provided it can be done. Some revisions are done with micro-code, which is a sort of software that can be loaded onto the chip. (In Windows XP Device Manager, I see there is a microcode driver.) I have no idea how that could fix anything. Redoing the thing without the patches costs too much and takes too long. Therefore the second production version, when they get around to it, is always the good one, the one the engineers really wanted to make.