So I was just getting into Anand's latest article, AMD Athlon II X4 620 & 630: The First $99 Quad Core CPU, and the first thing that struck me when I saw the die shot is that the two cores on the bottom (in Anand's dieshot orientation) are smaller that the two on the top, but about 3% linearly from my crude pixelated guestimates.
http://i272.photobucket.com/al...I_X4_Die_annotated.jpg
You can really see the delineation well along the horizontal axis of the two cache blocks for the left-most cores.
Assuming this isn't some weird trickery of the camera angle or some such, doesn't this seem kinda odd to have the cores physically scaled to occupy differing amounts of silicon real-estate? That has got to make verification all the more challenging, as well as interesting to handle the inter-core clock-skew and so on.
If it was posted by anyone other than Anand we'd all cry photoshop, but I doubt Anand's sources here are anyone other than AMD so I'm pretty sure we can rule out this being a faked dieshot photo. Are there other examples in recent times of asymmetric core size scaling in MPU's?
I can fathom some of the benefits to doing so (maximize use of available real-estate budget), but all of those benefits come with serious trade-offs that I would have assumed until now had a foregone conclusion that the downside of the trade-offs outweighed the upside of the benefits. Apparently that is not the case for the Athlon X4 as we are looking at the proof with our own eyes.
http://i272.photobucket.com/al...I_X4_Die_annotated.jpg
You can really see the delineation well along the horizontal axis of the two cache blocks for the left-most cores.
Assuming this isn't some weird trickery of the camera angle or some such, doesn't this seem kinda odd to have the cores physically scaled to occupy differing amounts of silicon real-estate? That has got to make verification all the more challenging, as well as interesting to handle the inter-core clock-skew and so on.
If it was posted by anyone other than Anand we'd all cry photoshop, but I doubt Anand's sources here are anyone other than AMD so I'm pretty sure we can rule out this being a faked dieshot photo. Are there other examples in recent times of asymmetric core size scaling in MPU's?
I can fathom some of the benefits to doing so (maximize use of available real-estate budget), but all of those benefits come with serious trade-offs that I would have assumed until now had a foregone conclusion that the downside of the trade-offs outweighed the upside of the benefits. Apparently that is not the case for the Athlon X4 as we are looking at the proof with our own eyes.