AMD and EUV

[Idontcare]

http://www.amd.com/us-en/Corpo...104_543~123954,00.html

This is really good news, I had not expected AMD and IBM to be this far along in practical hands-on application of EUV. Good news indeed.

 

[SsupernovaE]

Is Intel working on EUV? What do they have up their sleeve for the next five to 10 years

 

[CTho9305]

Is Intel working on EUV? What do they have up their sleeve for the next five to 10 years

They've been working on it for about a decade. I got this link about Intel's EUV work from idontcare.

 

[Cogman]

Sooo.... Enlighten me. I kind of can guess that EUV is Lithography with Ultra violet lights, but what are the benifits/drawbacks ect. The news item sounded exciting but I'm a bit lost on what I should be excited over.

 

[Duvie]

Lithography is how highly complex chip designs with millions of transistors, like microprocessors, are transferred onto the silicon wafer for the many layers required to build a chip. As chip designers continue to add functions and increase the performance of their products, making the transistors smaller and smaller makes more transistors available within a given area. How small transistors and the metal lines that connect them can be made is directly related to the wavelength of light that is used to project a chip design onto a wafer. EUV lithography uses a wavelength of 13.5 nm, significantly shorter than today?s 193 nm lithography techniques, allowing the traditional scaling of chip feature sizes to continue

I think this explains it....

I would assume that standard lithography used now may be coming to an end of its useful life, and as Intel/AMD and other chip makers continue to reduce the process sizes the newer method with its signiificantly shorter wavelength will be needed.

This basically is important as a hurdle to continue the process. More and more transistors, complexed layout, in an ever decreasing package size....

 

[CTho9305]

The sharpness of an image you can project with light is limited by the light's wavelength. Currently, lithography is done by shining light with a wavelength of 193nm (still UV - visible light is 400-700nm) at the wafer. As you draw shapes that are smaller and smaller relative to the wavelength of the light, the shapes get blurrier or can disappear altogether. To avoid this, there are workarounds used (google "phase shift masking" for details), but they come with significant downsides. In particular, the shapes that you can print become very limited, and for the very smallest shapes, you can only draw them reliably if they look exactly like their surroundings (so, evenly spaced lines of the same length show up well; lines with different spacings aren't as manufacturable). Partly because of this, modern CPU caches have to have an extra row and column of dummy cells (they store no data) at each end of their SRAM arrays, because the last row and column have much higher variability (the dummy cells look like normal SRAM cells, so the next row / column in see surroundings that look consistent).

Going to a shorter wavelength of light alleviates these challenges; if you can get a wavelength that's smaller than the features you're drawing, a whole bunch of problems just go away completely. EUV uses a wavelength of 13nm, which would make lithography for 32, 22, and 15nm nodes fantastic (ignoring all the other challenges we're running into )

Wikipedia article on photolithography, resolution section

Wikipedia article on phase shift masking

 

[Cogman]

So if I am understanding this correctly, currently AMD has some problems with the manufacturing of their cpus (as evident by the small L2 cache, and various errata and overclocking inability). But they are using a 193nm wavelength light. So if they can shrink down to this 13nm wavelength light, we are looking at much higher production yields, easier transitions with die shrinks and possibly more reliable processors all around, correct?

Thats awesome, I hope they get this down quickly.

 

[CTho9305]

Originally posted by: Cogman
So if I am understanding this correctly, currently AMD has some problems with the manufacturing of their cpus (as evident by the small L2 cache, and various errata and overclocking inability). But they are using a 193nm wavelength light. So if they can shrink down to this 13nm wavelength light, we are looking at much higher production yields, easier transitions with die shrinks and possibly more reliable processors all around, correct?

Thats awesome, I hope they get this down quickly.

Everybody uses 193nm. What you said applies to all semiconductor companies using processes better than 180nm / 0.18um (i.e. the first socket A Athlons, mid-range P3s, and newer). Cache sizes are generally not going to be defect-limited, since cache handles defects well (you don't have to throw out the chip when there's a defect in the cache - caches can repair up to a certain number of defects, even without reducing capacity). IIRC the AMD TLB erratum is unrelated to manufacturing.

 

[Cogman]

But the overclocking is [edit, you just said cache is unrelated.. woops ]. I know that everyone uses the same light wavelength, but with a different spin on it. For example intel's manufacturing process is different and in some ways must be more robust then AMD's because they don't seem to be having problems with their die shrinks ect.

I know that overclocking might be a bad measure, but I think a big part (and could be wrong) of it is how successful the manufacturing process can be measured by how fast a cpu can be clocked. IE, better lines conduct electricity better and leak less. Am I way off with this? It just seems like when AMD starts marketing 3 core processors where one of the cores was basically a bum core and they disabled it, they are have manufacturing problems.

BTW thanks for the responses, I always love to learn more about this stuff.

 

[CTho9305]

Originally posted by: Cogman
But the overclocking is [edit, you just said cache is unrelated.. woops ]. I know that everyone uses the same light wavelength, but with a different spin on it. For example intel's manufacturing process is different and in some ways must be more robust then AMD's because they don't seem to be having problems with their die shrinks ect.

And yet Penryn was delayed? (Given the choice between manufacturing 100 C2Q's per wafer on 65nm and 200C2Q's per wafer on 45nm -- for less than 2x the cost to you, what kind of idiot would stick to 65nm just because competitors aren't competitive at the moment?) Were there problems with Brisbane (65nm shrink)? Barcelona/Phenom weren't on a new process. Are there problems with whatever the 45nm quad cores are?

I know that overclocking might be a bad measure, but I think a big part (and could be wrong) of it is how successful the manufacturing process can be measured by how fast a cpu can be clocked. IE, better lines conduct electricity better and leak less. Am I way off with this? It just seems like when AMD starts marketing 3 core processors where one of the cores was basically a bum core and they disabled it, they are have manufacturing problems.

You're pretty far off. You can build a crappy CPU on a fantastic manufacturing process (see P4, for example), and you can build a good CPU on a less-fantastic manufacturing process (see AMD's chip during the period where Intel was getting stomped AND Intel was ahead by a process node... or maybe the more recent Itanium processors (which are still 90nm IIRC)). The actual design of the chip has a very significant effect on the quality of the result.

When it comes to tri-cores, unless you know how many of the dies have to be sold as tri-cores, you can't really tell whether there are 99k quad cores and 1k tri-cores, or 10k quad cores and 90k tri-cores (like Cell and its 7-of-8 working DSPs ). Marketing hype does not always correlate with production volumes.

When it comes to overclockability, high OC potential could be an indicator of bad things. Obviously Intel would want to sell the chips at the highest reliable speed. For all we know, Core 2 chips are so OCable because Intel couldn't get them to last long enough at higher operating points and all the OC'd chips will start dying after 3 years. Or, non-fatal wear-out mechanisms may start to drastically reduce their OC headroom after they've aged for a few years. Or maybe the power just goes up too much and OEM's aren't willing to spend enough on heatsinks to cool them when they run faster.

I'm not saying any of this is the case. I'm just playing devil's advocate.

 

[Idontcare]

Originally posted by: Cogman
So if I am understanding this correctly, currently AMD has some problems with the manufacturing of their cpus (as evident by the small L2 cache, and various errata and overclocking inability).

The subject matter you touch on here is unrelated to the process technology we are talking about.

Originally posted by: Cogman
So if they can shrink down to this 13nm wavelength light, we are looking at much higher production yields, easier transitions with die shrinks and possibly more reliable processors all around, correct?

It's purely about enabling die shrinks. Nothing is easy, and EUV makes nothing easier, but it does make the impossible become possible (16nm node with 193nm traditional litho = impossible in a binary sense).

If EUV is not ready for production circa 2011 in order to support R&D efforts to create the 16nm node then 16nm node timeline could be in jeopardy of being pushed back from the 2013 ETA.

These things are called "brick walls" in the industry (google ITRS if interested).

 

[Viditor]

Originally posted by: Idontcare
http://www.amd.com/us-en/Corpo...104_543~123954,00.html

This is really good news, I had not expected AMD and IBM to be this far along in practical hands-on application of EUV. Good news indeed.

AMD first started demonstrating EUV phase-shift mask prototypes last year.
It is expected by most that AMD's upcoming Malta, NY Fab (article) should be operational with EUV by 2011 and 22nm shipments are slated for late 2012.

 

[Idontcare]

Originally posted by: Viditor

Originally posted by: Idontcare
http://www.amd.com/us-en/Corpo...104_543~123954,00.html

This is really good news, I had not expected AMD and IBM to be this far along in practical hands-on application of EUV. Good news indeed.

AMD first started demonstrating EUV phase-shift mask prototypes last year.
It is expected by most that AMD's upcoming Malta, NY Fab (article) should be operational with EUV by 2011 and 22nm shipments are slated for late 2012.

I must admit after having watched the less than noble actions of TI's executive management wrangle money from Texas for years and years over their RFAB (still an empty shell) that I am less than optimistic that AMD's executive management isn't doing the same foot-dragging with NY. It is an all too common play from the american management rulebook.

AMD's NY fab won't factor into anything I have to think or say about AMD until the day they actually ship for revenue product from the fab. But the mouthpieces giving their statements is a sign at least that AMD hasn't vacated from the plan yet.

EUV is spendy, big time spendy. ($180M estimated for production tools when they come available)

 

[Viditor]

Originally posted by: Idontcare

Originally posted by: Viditor

Originally posted by: Idontcare
http://www.amd.com/us-en/Corpo...104_543~123954,00.html

This is really good news, I had not expected AMD and IBM to be this far along in practical hands-on application of EUV. Good news indeed.

AMD first started demonstrating EUV phase-shift mask prototypes last year.
It is expected by most that AMD's upcoming Malta, NY Fab (article) should be operational with EUV by 2011 and 22nm shipments are slated for late 2012.

I must admit after having watched the less than noble actions of TI's executive management wrangle money from Texas for years and years over their RFAB (still an empty shell) that I am less than optimistic that AMD's executive management isn't doing the same foot-dragging with NY. It is an all too common play from the american management rulebook.

AMD's NY fab won't factor into anything I have to think or say about AMD until the day they actually ship for revenue product from the fab. But the mouthpieces giving their statements is a sign at least that AMD hasn't vacated from the plan yet.

EUV is spendy, big time spendy. ($180M estimated for production tools when they come available)

I think that NY is pretty much a foregone conclusion. I don't know if you actually caught the part where NY is giving AMD a $1.2 Billion incentive to build there...

And EUV isn't the only thing going on right now...I am still looking forward to see how well AMD does with their new immersion lithography at Fab 38. The second iteration of Shanghai is to be on immersion (Q1 09).

 

[Idontcare]

Originally posted by: Viditor
I think that NY is pretty much a foregone conclusion. I don't know if you actually caught the part where NY is giving AMD a $1.2 Billion incentive to build there...

And EUV isn't the only thing going on right now...I am still looking forward to see how well AMD does with their new immersion lithography at Fab 38. The second iteration of Shanghai is to be on immersion (Q1 09).

Would love to see it happen. I'd probably interview for a job