Discussion AM5 Socket Design, Integrated Heat Spreader

[Kedas]

There are some 'new' fake or not renders of AM5 here.
https://t.co/84T6wUjpQ2
For the sake of argument let's assume this is how it will look.

Is it possible that they increased the height of the IHS so they would have more freedom to stack with different heights below it?
Yes you IHS would need to have some 'levels' cut out (less than 0.5mm) but it may be easier than trying to get it all different dies on the same height.

Not sure where this would come into play but I guess if you have 3 different dies this may be a better idea.
Maybe when they add a (variable) HBM3 height it's much easier to have another set of IHS than having to add extra layer on the other dies to match it.

Maybe it's only thicker because they increased the TDP

 

[Joe NYC]

There are some 'new' fake or not renders of AM5 here.
https://t.co/84T6wUjpQ2
For the sake of argument let's assume this is how it will look.

Is it possible that they increased the height of the IHS so they would have more freedom to stack with different heights below it?
Yes you IHS would need to have some 'levels' cut out (less than 0.5mm) but it may be easier than trying to get it all different dies on the same height.

Not sure where this would come into play but I guess if you have 3 different dies this may be a better idea.
Maybe when they add a (variable) HBM3 height it's much easier to have another set of IHS than having to add extra layer on the other dies to match it.

Maybe it's only thicker because they increased the TDP

I came across an article today which described TSMC demonstration of a stack 12 high and the height of the entire stack was 600um, which is 0.6 mm. So the height of the stack is not a big deal.

 

[Ajay]

That rendering of the 'AM5' heatspreader has been around a while. What's new is the CPU retention mechanism being included.

 

[Hitman928]

I came across an article today which described TSMC demonstration of a stack 12 high and the height of the entire stack was 600um, which is 0.6 mm. So the height of the stack is not a big deal.

Do you have a link? 50 um height for each stack layer is pretty crazy. I imagine the yield on trying to actually stack them would be terrible as handling and placing a 50 um thick die accurately is not an easy task. To do it 12 times on top of one other would be extremely difficult I imagine.

Edit: Nevermind, I just saw they AT article on it. They are actually claiming <600 um which is just crazy. TSMC must have really spent a lot of R&D on their thinning and aligning process. I still question the commercial viability of such a configuration, but I am prepared to be proven wrong 🙂

Edit2: Just as an illustration, <50 um thickness is about half the thickness of a standard sheet of copy paper. So take that thickness with an x/y of half and inch or less (10 mm) and that is what you have to handle and 'perfectly' line up with a stack of 11 other sheets all on top of each other while handling something that will break if you let the edges roll up or shift around too much.

 

[Joe NYC]

Do you have a link? 50 um height for each stack layer is pretty crazy. I imagine the yield on trying to actually stack them would be terrible as handling and placing a 50 um thick die accurately is not an easy task. To do it 12 times on top of one other would be extremely difficult I imagine.

Edit: Nevermind, I just saw they AT article on it. They are actually claiming <600 um which is just crazy. TSMC must have really spent a lot of R&D on their thinning and aligning process. I still question the commercial viability of such a configuration, but I am prepared to be proven wrong 🙂

Edit2: Just as an illustration, <50 um thickness is about half the thickness of a standard sheet of copy paper. So take that thickness with an x/y of half and inch or less (10 mm) and that is what you have to handle and 'perfectly' line up with a stack of 11 other sheets all on top of each other while handling something that will break if you let the edges roll up or shift around too much.

Yes, the thickness, or should I say thinness is almost hard to believe. There was a video / explainer that compared it to thickness of paper.

A little lamish, but parts of it are informative:
The Bring Up: Computex 2021 and Revolutionary 3D Chiplets - YouTube

 

[Kedas]

I came across an article today which described TSMC demonstration of a stack 12 high and the height of the entire stack was 600um, which is 0.6 mm. So the height of the stack is not a big deal.

As I said we are talking about less than 0.5mm but I assume you don't want this difference to be bridged with more solder between IHS and die.