All AMD chips now at 65nm in Fab36

[Viditor]

Inq Article

"We hear heard that the transition to 65nm is going well, and currently 100 per cent of wafer starts are 65nm at Fab36"

Charlie D. rumour...if true, they're 3 months ahead of schedule.

 

[tommo123]

good news for everyone then. this gen i am with intel (amd last time around) and this might push the Q6600 price down a bit faster

 

[Phynaz]

Has anyone ever determined why Intel got a the correct 50% reduction in die size moving from 90nm to 65nm, and AMD did not?

 

[myocardia]

Originally posted by: Phynaz
Has anyone ever determined why Intel got a the correct 50% reduction in die size moving from 90nm to 65nm, and AMD did not?

It was Intel that had problems moving to 65nm, not AMD. In other words, it was just like the move from 130nm to 90nm; AMD made less mistakes.

 

[Phynaz]

Originally posted by: myocardia

Originally posted by: Phynaz
Has anyone ever determined why Intel got a the correct 50% reduction in die size moving from 90nm to 65nm, and AMD did not?

It was Intel that had problems moving to 65nm, not AMD. In other words, it was just like the move from 130nm to 90nm; AMD made less mistakes.

I didn't ask about problems, I asked about die size.

 

[nyker96]

but when brisbane first came out there was rumors that 65nm not going well, many of the review sites that tried OC bris didn't have much success so everyone is speculating the new process isn't too good.

 

[myocardia]

Originally posted by: Phynaz
I didn't ask about problems, I asked about die size.

That's strange, I haven't heard about either company making the wrong die size. What do you know that we don't?

 

[Phynaz]

Originally posted by: myocardia

Originally posted by: Phynaz
I didn't ask about problems, I asked about die size.

That's strange, I haven't heard about either company making the wrong die size. What do you know that we don't?

"Given perfect scaling, you'd expect a 65nm shrink of a 90nm core to be approximately 52% the size of the larger core. Looking at Brisbane, AMD went from 183 mm^2 with its 90nm Windsor core down to 126 mm^2 at 65nm, making the newer core almost 69% the size of the older one. "

AMD missed by 25%. I was just wondering what pieces they didn't shrink.

Anandtech Article

 

[myocardia]

Originally posted by: Phynaz
"Given perfect scaling, you'd expect a 65nm shrink of a 90nm core to be approximately 52% the size of the larger core. Looking at Brisbane, AMD went from 183 mm^2 with its 90nm Windsor core down to 126 mm^2 at 65nm, making the newer core almost 69% the size of the older one. "

AMD missed by 25%. I was just wondering what pieces they didn't shrink.

Anandtech Article

My guess would be the on-die memory controller. But, it's pretty normal for die shrinks to be larger than they should be, since alot of the time, they add something that they don't tell us about right at first, or that doesn't benefit us at first, like SSE, for instance.

 

[CTho9305]

Originally posted by: Phynaz

Originally posted by: myocardia

Originally posted by: Phynaz
I didn't ask about problems, I asked about die size.

That's strange, I haven't heard about either company making the wrong die size. What do you know that we don't?

"Given perfect scaling, you'd expect a 65nm shrink of a 90nm core to be approximately 52% the size of the larger core. Looking at Brisbane, AMD went from 183 mm^2 with its 90nm Windsor core down to 126 mm^2 at 65nm, making the newer core almost 69% the size of the older one. "

AMD missed by 25%. I was just wondering what pieces they didn't shrink.

Anandtech Article

Array structures (SRAMs - caches, register files) scale poorly. As the process shrinks, device variations become more of a problem, and structures that are sensitive to device parameters have to be margined more and more. As a result, they don't shrink as well, and/or they get slower. This image is of 130nm and 90nm CPUs; if you can find a die photo of a 65nm CPU to compare, you could overlay them and see how structures scaled relative to each other. There are other factors, but they probably don't count for as much of the poor scaling.

 

[Viditor]

Originally posted by: Phynaz
Has anyone ever determined why Intel got a the correct 50% reduction in die size moving from 90nm to 65nm, and AMD did not?

It's not a "correct" anything, it's that the vast majority of Intel's transistor increase went to cache...and Intel can make some of the densest cache there is.
It has nothing to do with the process though...

 

[formulav8]

Originally posted by: Phynaz
Has anyone ever determined why Intel got a the correct 50% reduction in die size moving from 90nm to 65nm, and AMD did not?

My opinion is that the 65nm core has More logic in it that AMD evidentally disabled and not mentioning anything about it. A old die shot of Revision 'G' shows a couple small area's that looked to originally get a couple tweaks (It appeared to be a legit die shot, although i proabably couldn't tell unless it was very obvious). Things may not have worked so well on the 65nm process, so AMD disabled the transisters, and therefore didn't advertise that the 65nm core has more transistors than 90nm but they are dormant.

That is all my opinion though. I guess we won't ever know exactly until AMD says something.


Jason

 

[CTho9305]

Originally posted by: formulav8

Originally posted by: Phynaz
Has anyone ever determined why Intel got a the correct 50% reduction in die size moving from 90nm to 65nm, and AMD did not?

My opinion is that the 65nm core has More logic in it that AMD evidentally disabled and not mentioning anything about it. A old die shot of Revision 'G' shows a couple small area's that looked to originally get a couple tweaks (It appeared to be a legit die shot, although i proabably couldn't tell unless it was very obvious). Things may not have worked so well on the 65nm process, so AMD disabled the transisters, and therefore didn't advertise that the 65nm core has more transistors than 90nm but they are dormant.

That is all my opinion though. I guess we won't ever know exactly until AMD says something.


Jason

Are you basing that on this image? There's a much higher-resolution pic of dual core 65nm CPUs at this AMD site (click "AMD Processors and Wafers", and it's the top image in the second column - click "JPG" and download the full 4992*3329px image...).

 

[Viditor]

BTW, there is something else in that blurb that Charlie says...

"We also hear that contrary to rumours floating about, yields are not in the toilet, but it may be for others trying to push out 65nm"

IMHO, these rumours are about the parts from "the company formerly known as ATI"...
Note that they are Fabbed at TSMC and NOT made by AMD themselves (a fact that many forget).

 

[Keysplayr]

90nm to 65nm is not just an optical shrink. redesign is necessary. Things change. 90nm to 80nm would be a direct optical shrink. You can figure out the percentages there if you want.

 

[coldpower27]

Originally posted by: keysplayr2003
90nm to 65nm is not just an optical shrink. redesign is necessary. Things change. 90nm to 80nm would be a direct optical shrink. You can figure out the percentages there if you want.

CPU never shrink by their theoretical optical shrink values. Even's Intel's Cedar Mill at 81mm2 is a tad bigger then it ought to be from the Prescott-2M 135mm2.

However Windsor-512 to Brisbane, was still poor by average optical shrink standards. At any rate, Barcelona has decent transistor density considering for the 65nm process given the die size and transistor count as well as factoring in how much core logic it needs.

This is interesting though regarding Fab 36 output, it would mean the remainder of the 90nm X2's are coming out of Fab 30, as it winds down production.

 

[Viditor]

Originally posted by: coldpower27

Originally posted by: keysplayr2003
90nm to 65nm is not just an optical shrink. redesign is necessary. Things change. 90nm to 80nm would be a direct optical shrink. You can figure out the percentages there if you want.

CPU never shrink by their theoretical optical shrink values. Even's Intel's Cedar Mill at 81mm2 is a tad bigger then it ought to be from the Prescott-2M 135mm2.

However Windsor-512 to Brisbane, was still poor by average optical shrink standards. At any rate, Barcelona has decent transistor density considering for the 65nm process given the die size and transistor count as well as factoring in how much core logic it needs.

This is interesting though regarding Fab 36 output, it would mean the remainder of the 90nm X2's are coming out of Fab 30, as it winds down production.

It is interesting...but to keep in perspective, they are saying wafer-ins, not wafer-outs. So we will still have another 3 months of tapering output @90nm from Fab 36
Also, don't forget that Chartered is fully capable @90nm as well as 65nm for overflow...

As to Fab 30's conversion, I seem to recall that it should be happening about now...
They are converting it to 45nm immersion, and the first wafer-ins are to be Jan 08. Though they also said that output will be reduced during the conversion but never stopped completely.

 

[SexyK]

Originally posted by: myocardia

Originally posted by: Phynaz
Has anyone ever determined why Intel got a the correct 50% reduction in die size moving from 90nm to 65nm, and AMD did not?

It was Intel that had problems moving to 65nm, not AMD. In other words, it was just like the move from 130nm to 90nm; AMD made less mistakes.

What problems did Intel have moving to 65nm? Intel's transition to 90nm was rocky because of the excess leakage which was only compounded by the Prescott design. However, AFAIK Intel's transition to 65nm was one of the most successful process shrinks they've ever made. Feel free to correct me if I'm wrong.

 

[SparkyJJO]

Originally posted by: nyker96
but when brisbane first came out there was rumors that 65nm not going well, many of the review sites that tried OC bris didn't have much success so everyone is speculating the new process isn't too good.

I've been seeing reports of 3600+ brisbanes hitting 3GHz (or a little more sometimes) over at XS. Doesn't sound bad to me.