Question Alder Lake - Official Thread

[Hulk]

With the release of Alder Lake less than a week away and the "Lakes" thread having turned into a nightmare to navigate I thought it might be a good time to start a discussion thread solely for Alder Lake.

 

[jpiniero]

Intel 65W Alder Lake-S pricing has been leaked, 6-core CPUs to cost 180-240 USD, 4-core 110-140 USD - VideoCardz.com

BestBuy leaks 12th Gen Core non-K “Alder Lake-S” pricing It appears that a large US retailer has now confirmed the pricing for the upcoming 12th Gen Core CPUs. Unfortunately, not all SKUs have been listed by BestBuy, which could either mean that some SKUs have delayed shipment, or that not all...

videocardz.com

12400F's MSRP might be $179.

 

[dullard]

Intel 65W Alder Lake-S pricing has been leaked, 6-core CPUs to cost 180-240 USD, 4-core 110-140 USD - VideoCardz.com

BestBuy leaks 12th Gen Core non-K “Alder Lake-S” pricing It appears that a large US retailer has now confirmed the pricing for the upcoming 12th Gen Core CPUs. Unfortunately, not all SKUs have been listed by BestBuy, which could either mean that some SKUs have delayed shipment, or that not all...

videocardz.com

12400F's MSRP might be $179.

Thanks. If you click on the BestBuy link, then click on a processor, then click the specifications, then I think that is the first confirmation of base and turbo speeds that I've seen. The rest that I've seen have been guesses.

 

[Heartbreaker]

HWUB investigates if you should disable e-cores to play games. Short Answer: No.

 

[Hulk]

One thing about Alder Lake I've noticed that hasn't been discussed is availability. This was definitely not a paper launch on Intel's part. Alder has been in stock everywhere in all varieties. Looks like they have the 10ESF node going well. And if they are a good supply of high end parts I'm sure there are plenty of "broken" ones ready for the general release.

I'm hoping that bodes well for ARC when it releases.

 

[Heartbreaker]

I'm hoping that bodes well for ARC when it releases.

I believe they are using TSMC for their first ARC consumer GPUs, so success of the in house process doesn't factor. But it is good that they have it running well.

 

[Hulk]

I believe they are using TSMC for their first ARC consumer GPUs, so success of the in house process doesn't factor. But it is good that they have it running well.

Would have been nice if they could have moved those 14++++++ fabs to produce a bunch of lower end ARC GPU's. If the performance was just decent they could probably sell all they could produce if the price was right, which ain't hard considering GPU pricing these days!

 

[Hitman928]

HWUB investigates if you should disable e-cores to play games. Short Answer: No.

Seems like it's more on a game to game basis but with the majority of newer titles preferring the E-cores disabled. With that said, the 12900k is obviously plenty fast enough either way. A lower powered ADL with 4/6P+HT with 4E would be a much more interesting comparison.

 

[igor_kavinski]

Intel Core i9-12900KS pre-binned CPU with 5.2 GHz all-core frequency allegedly in the works - VideoCardz.com

If this actually materializes, it should become the new power hog champion at stock clocks.

 

[coercitiv]

Seems like it's more on a game to game basis but with the majority of newer titles preferring the E-cores disabled. With that said, the 12900k is obviously plenty fast enough either way. A lower powered ADL with 4/6P+HT with 4E would be a much more interesting comparison.

There's also overclocking to be considered. As Steve already mentions towards the end of the video, on Alder Lake the ring multiplier is limited to 36X when E-cores are enabled and under load. Those looking to overclock will probably want to push the ring bus as well.

 

[coercitiv]

A sample voltage curve for P-cores, E-cores and Ring derived from adaptive voltage readings on a 12700K. Source is here.



This should be of special interest for @DrMrLordX in relation to previous discussions of inefficiencies in the single voltage rail model for ADL P-cores, E-cores, and Ring.

Notice how E-core @ 3.8Ghz requires roughly the same voltage as P-core at 4.7GHz. Based on this we can conclude P-core voltage isn't introducing large inefficiencies for E-cores in MT workloads as long as power limits aren't high enough to allow P-core clocks higher than 4700Mhz. For example running CB23 on 12700K with PL1 = PL2 = 150W results in 4.5Ghz on P-cores and 3.5Ghz on E-cores. That's ~1.15V versus ~1.1V.

At 200W we're bound to start wasting power, but at the same time... 200W+ is a monument of inefficiency anyway.

 

[Ajay]

A sample voltage curve for P-cores, E-cores and Ring derived from adaptive voltage readings on a 12700K. Source is here.

View attachment 54780

This should be of special interest for @DrMrLordX in relation to previous discussions of inefficiencies in the single voltage rail model for ADL P-cores, E-cores, and Ring.

Notice how E-core @ 3.8Ghz requires roughly the same voltage as P-core at 4.7GHz. Based on this we can conclude P-core voltage isn't introducing large inefficiencies for E-cores in MT workloads as long as power limits aren't high enough to allow P-core clocks higher than 4700Mhz. For example running CB23 on 12700K with PL1 = PL2 = 150W results in 4.5Ghz on P-cores and 3.5Ghz on E-cores. That's ~1.15V versus ~1.1V.

At 200W we're bound to start wasting power, but at the same time... 200W+ is a monument of inefficiency anyway.

Since i haven’t been paying attention, at what frequency is the ring running at?

 

[DrMrLordX]

Notice how E-core @ 3.8Ghz requires roughly the same voltage as P-core at 4.7GHz.

That's odd. I wouldn't have expected Gracemont to require such high voltages. Sadly you're still suffering at anything past 4.7 GHz which might explain why Alder Lake overall gains so much efficiency at lower clocks/power targets.

 

[coercitiv]

Since i haven’t been paying attention, at what frequency is the ring running at?

For the 12700K the ring runs at 4.6Ghz while E-cores are idle and drops down to 3.6Ghz when E-cores are working. I believe the 12600K and 12900K run the same or similar clocks.

 

[Asterox]

Cool CPU cooler, or the best new Intel stock RH1 CPU cooler.

https://twitter.com/x/status/1473312961657667585

 

[JoeRambo]

There seems to be problem with Windows 11 scheduler when E cores are disabled - loads are not sticking to single core, but moved around HT threads and overall around.
At least in my testing with fixed 5Ghz clocks. Need someone with 12400F or other CPU with run CB23 with custom thread number = 6 and watch task manager. Note the score and disable HT and run same 6 threads and check difference.

 

[igor_kavinski]

That's odd. I wouldn't have expected Gracemont to require such high voltages. Sadly you're still suffering at anything past 4.7 GHz which might explain why Alder Lake overall gains so much efficiency at lower clocks/power targets.

Raptor Lake's 16 E-cores will likely be running at a lower voltage so possibly lower clocks? Or is Intel going to keep their voltage same as Alder Lake but pump up Raptor Lake's P-cores with more voltage to reach 5.5 GHz?

 

[Doug S]

For the 12700K the ring runs at 4.6Ghz while E-cores are idle and drops down to 3.6Ghz when E-cores are working. I believe the 12600K and 12900K run the same or similar clocks.

Interesting, so the inter core bandwidth between P cores is slowed down when E cores are active? That seems ... suboptimal.

 

[Exist50]

Interesting, so the inter core bandwidth between P cores is slowed down when E cores are active? That seems ... suboptimal.

I heard that the latest stepping (C3, maybe?) closes the gap by a couple hundred MHz. Hoping someone can get ahold of a sample to test.

 

[Ajay]

Interesting, so the inter core bandwidth between P cores is slowed down when E cores are active? That seems ... suboptimal.

And it's a really weird multiplier. Seems like something is off, or Intel is really using an asynchronous 'stop' between the two rings.

 

[scannall]

And it's a really weird multiplier. Seems like something is off, or Intel is really using an asynchronous 'stop' between the two rings.

It's Intel's first effort at this. Of course it will be sub-optimal. And that's fine, you can't take a second step without the first. Also, they don't control their software and OS stack though they do have quite a bit of influence.

Intel: Hey MS, we're releasing a big/LITTLE CPU. Aren't you excited?

MS: Seriously? Please tell me you're kidding.

Intel: No, it'll be great. And you have plenty of time. Really. October 2021 is fine.

MS: Seriously....

Intel: Hey, Apple figured it out. Can't you? Lame or something?

MS: And they figured out great performance with less draw than a pizza oven. Lame or something?

 

[deasd]

B660 price, more expensive than expected?

https://twitter.com/x/status/1473621607994507269

 

[IntelUser2000]

Interesting, so the inter core bandwidth between P cores is slowed down when E cores are active? That seems ... suboptimal.

The ring bus bandwidth is actually the L3 bandwidth for the cores. So having a 4.7GHz ring would mean it would be clocked faster than the E cores themselves.

Don't think I ever heard of the caches clocking faster than the CPU cores. Since the E cores have a different design philosophy and it's their first successful(first implementation is Lakefield) hybrid implementation, the E cores may simply not be capable of having the caches clocked faster.

If we also take the speculation that Alderlake was similar to Broadwell and desktop is a side effect, at the mobile frequencies the ring bus issue would be negligible since the clocks are way lower.

 

[DrMrLordX]

Raptor Lake's 16 E-cores will likely be running at a lower voltage so possibly lower clocks? Or is Intel going to keep their voltage same as Alder Lake but pump up Raptor Lake's P-cores with more voltage to reach 5.5 GHz?

Raptor Lake should have separate voltage domains for the P and E cores. It would make some sense to clock the E cores a little lower when there are more of them (and to run lower volts) assuming Intel plans on using the E cores only for MT throughput. As to whether they'll need more voltage to up P core clocks . . . we'll see.

 

[Hulk]

A sample voltage curve for P-cores, E-cores and Ring derived from adaptive voltage readings on a 12700K. Source is here.

View attachment 54780

This should be of special interest for @DrMrLordX in relation to previous discussions of inefficiencies in the single voltage rail model for ADL P-cores, E-cores, and Ring.

Notice how E-core @ 3.8Ghz requires roughly the same voltage as P-core at 4.7GHz. Based on this we can conclude P-core voltage isn't introducing large inefficiencies for E-cores in MT workloads as long as power limits aren't high enough to allow P-core clocks higher than 4700Mhz. For example running CB23 on 12700K with PL1 = PL2 = 150W results in 4.5Ghz on P-cores and 3.5Ghz on E-cores. That's ~1.15V versus ~1.1V.

At 200W we're bound to start wasting power, but at the same time... 200W+ is a monument of inefficiency anyway.

I have a few questions regarding this Voltage vs. Frequency plot. Please excuse my lack of knowledge here. Consider V=IR, how does this Frequency vs. Voltage plot compare to a Power vs. Frequency plot? At the end of the day it's the power we're concerned about, right?

If the E core requires 1.2V at 3.8GHz and the P requires 1.2V at ~4.7GHz, how does that relate to power usage? At the end of the day we need to know the current to know power right?

 

[Asterox]

B660 price, more expensive than expected?

https://twitter.com/x/status/1473621607994507269

Severe headache, huh lol blah. When you compare/price=performance, "old Intel 1200 socket motherboards" or new 1700 boards with cheep "MSI B550M PRO-VDH WIFI garbage for 125$".

Four Cheap Micro ATX B550 Motherboards Tested: Low Price, Big Value?

These cheap B550 boards are light on the wallet, but how do they perform with a 3900X?

www.tomshardware.com