Airmont vs Silvermont info

[Arachnotronic]

I found this link on the web showing some changes Intel made in going from Silvermont to Airmont: http://users.atw.hu/instlatx64/SilvermontVSAirmont.txt

Apparently Intel made the re-order buffer larger (48 entries up from 32 in Silvermont) in Airmont and the number of 4KB DTLB entries is increased from 128 in Silvermont to 256 in Airmont. L2 latency goes up a bit from 14 cycles in Silvermont to 15 in Airmont.

Good Silvermont overview here: http://www.realworldtech.com/silvermont/1

 

[VirtualLarry]

and the number of 4KB DTLB entries is increased from 128 in Silvermont to 256 in Airmont. L2 latency goes up a bit from 14 cycles in Silvermont to 15 in Airmont.

Are they increasing the size of the cache too, with those modifications?

 

[Arachnotronic]

Are they increasing the size of the cache too, with those modifications?

No, AFAIK, all cache sizes in Airmont are identical to those in Silvermont.

 

[VirtualLarry]

If they: 1) Increased L2 latency, but 2) didn't increase L2 size, does that then mean 3) that they might look to increase clockspeed?

 

[CHADBOGA]

I found this link on the web showing some changes Intel made in going from Silvermont to Airmont: http://users.atw.hu/instlatx64/SilvermontVSAirmont.txt

Apparently Intel made the re-order buffer larger (48 entries up from 32 in Silvermont) in Airmont and the number of 4KB DTLB entries is increased from 128 in Silvermont to 256 in Airmont. L2 latency goes up a bit from 14 cycles in Silvermont to 15 in Airmont.

Good Silvermont overview here: http://www.realworldtech.com/silvermont/1

So what performance gains do these changes bring? :hmm:

 

[Exophase]

I wonder if the depth of the reservation stages and rename files have been increased as well to accommodate the larger ROB, or if they found that it was relatively undersized in relation and therefore worth increasing in isolation. A typical run of 32 instructions in the ROB should require somewhat less than 32 rename registers by virtue of branch, compare, and store instructions not needing new registers allocated.

Likewise, the ROB was pretty small for the size of the schedulers. Cotex-A15 for example also has a 128 entry ROB but only a somewhat higher number of 8-entry distributed schedulers.

 

[Dresdenboy]

So what performance gains do these changes bring? :hmm:

The L2 latency increase shouldn't do much. DTLB increase helps a bit with mem intensive software. The ROB might cause an avg. 3-5% performance increase on its own.

But numbers given in papers are also influenced by the other features of the microarchitectures.

 

[Face2Face]

If they: 1) Increased L2 latency, but 2) didn't increase L2 size, does that then mean 3) that they might look to increase clockspeed?

Comparing the two top ATOM models -

We have a slight increase of base frequency, but the Turbo clock speed is identical. Even the L2 cache sizes appear to be the same. Memory frequency has also increased, which should help both CPU and GPU. CPC, I don't think we're going to see a tangible difference between the two, CPU wise.

The biggest change in the Cherry Trail is it's Broadwell (Gen 8) based GPU. Though GPU frequency has dropped a little, the Architecture is faster CPC and the number of EUs has tripled (on Cherry Trails top model).

 

[waltchan]

I'm not too optimistic with upcoming Airmont. IF the Braswell Celeron N3150 quad-core only receives 372 single-thread score from 527 in Celeron J1900, chances are Airmont will return back to 500 where Bay Trail first started.

 

[Arachnotronic]

I'm not too optimistic with upcoming Airmont. IF the Braswell Celeron N3150 quad-core only receives 372 single-thread score from 527 in Celeron J1900, chances are Airmont will return back to 500 where Bay Trail first started.

Airmont cores are used in Braswell.