I had some technical questions about flash memory that the OCZ forum was not really able to answer: here
Here goes...
As it is defined, flash memory is "0" in a programmed state and "1" in an erased state.
http://img23.imageshack.us/my.php?image=flashnwz.png
This is true for both NAND and NOR flash. SLC only has these two states, while MLC has four:
Value State
00 Fully Programmed
01 Partially Programmed
10 Partially Erased
11 Fully Erased
(reference)
Now, flash memory has to be programmed to write bits. To do so, the bit must be in an erased state. A block can be read or written (programmed) on a page basis, but erasing must be done by a block basis (see the anandtech article). Hence, drives achieve a "steady state" performance upon which any additional written data has to trigger an erase command first (a bit simplistic, but it'll suffice for now).
Questions:
1. How does the SSD know that a page is writable (i.e. fully erased)? Intel says:
"SSDs all have what is known as an ?Indirection System? ? aka an LBA allocation table (similar to an OS file allocation table)...."
If this is true, then writing any erase pattern (zeros, ones, or a mix) with something like Eraser will not restore "free space" to programmable space, because each block is "addressed" as erasable or programmable by the indirection system. Now if there's some way to access this indirection data, then this should not be a problem. If I am reading this wrong, then writing 1's in eraser should restore the drive to pre-steady state performance in free space regions.l
2. Related: How does TRIM differ from simply writing a bit pattern to a particular block in the SSD?
3. Isn't it horrendously bad for this indirection region to be located on flash itself? Whenever a block is erased or programmed, that block has to be written, AS WELL AS the information in the indirection region that indicates whether or not that block has been erased or programmed.
Can anyone try different bit patterns in Eraser (or similar) on a "steady state" SSD to confirm some of the above observations?
Here goes...
As it is defined, flash memory is "0" in a programmed state and "1" in an erased state.
http://img23.imageshack.us/my.php?image=flashnwz.png
This is true for both NAND and NOR flash. SLC only has these two states, while MLC has four:
Value State
00 Fully Programmed
01 Partially Programmed
10 Partially Erased
11 Fully Erased
(reference)
Now, flash memory has to be programmed to write bits. To do so, the bit must be in an erased state. A block can be read or written (programmed) on a page basis, but erasing must be done by a block basis (see the anandtech article). Hence, drives achieve a "steady state" performance upon which any additional written data has to trigger an erase command first (a bit simplistic, but it'll suffice for now).
Questions:
1. How does the SSD know that a page is writable (i.e. fully erased)? Intel says:
"SSDs all have what is known as an ?Indirection System? ? aka an LBA allocation table (similar to an OS file allocation table)...."
If this is true, then writing any erase pattern (zeros, ones, or a mix) with something like Eraser will not restore "free space" to programmable space, because each block is "addressed" as erasable or programmable by the indirection system. Now if there's some way to access this indirection data, then this should not be a problem. If I am reading this wrong, then writing 1's in eraser should restore the drive to pre-steady state performance in free space regions.l
2. Related: How does TRIM differ from simply writing a bit pattern to a particular block in the SSD?
3. Isn't it horrendously bad for this indirection region to be located on flash itself? Whenever a block is erased or programmed, that block has to be written, AS WELL AS the information in the indirection region that indicates whether or not that block has been erased or programmed.
Can anyone try different bit patterns in Eraser (or similar) on a "steady state" SSD to confirm some of the above observations?
