Traditionally, a Northbridge exists between the memory bus and the CPU. The rate at which data is transferred between the memory and CPU is known as the front side bus. However, the Athlon64?s memory controller is on-die, and as such, has no Northbridge, nor a front side bus. The Athlon64?s have two independent buses; one between the memory and the on-die controller, and another bus that communicates with the other system devices- the HyperTransport bus. The CPU?s clock speed is determined by the HyperTransport speed multiplied by a clock multiplier, which is why it?s often suggested to view the HyperTransport bus as if it were the front side bus. However, this is about where the similarities between the two diverge. Traditionally, the memory speed is derived off of the front side bus, and can be manipulated by FSB/memory ratios. In contrast, in the A64, memory speed is derived off of the CPU speed in CPU/memory ratios. This is why it?s rather inaccurate to say that the memory is ever running ?synchronously.? The memory is always running asynchronously with respect to the CPU speed, off of which it?s derived. How fast it?s running with respect to the HyperTransport bus does not matter at all. There is no latency hit in running the memory slower than the HyperTransport bus. The HyperTransport bus? effective speed is determined by an LDT(Lighting data transport) multiplier. While the front side bus could?ve been traditionally double or quad-pumped, the HyperTransport?s effective data rate can be anywhere from 1x to 5x it?s speed on the CPU.
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