A Survey Of Architectural Techniques for Managing Process Variation
Accepted in ACM Computing Surveys 2016
Process variation --deviation in parameters from their nominal specifications-- threatens to slow down and even pause technological scaling and mitigation of it is the way to continue the benefits of chip miniaturization. In this paper, we present a survey of architectural techniques for managing process variation (PV) in modern processors.
We review nearly 125 papers that discuss PV management techniques in CPU, GPU, different processor components (cache, main memory, processor core) and different memory technologies (SRAM, DRAM, eDRAM, NVM) etc.
Accepted in ACM Computing Surveys 2016
Process variation --deviation in parameters from their nominal specifications-- threatens to slow down and even pause technological scaling and mitigation of it is the way to continue the benefits of chip miniaturization. In this paper, we present a survey of architectural techniques for managing process variation (PV) in modern processors.
We review nearly 125 papers that discuss PV management techniques in CPU, GPU, different processor components (cache, main memory, processor core) and different memory technologies (SRAM, DRAM, eDRAM, NVM) etc.
