A Survey of Techniques for Architecting and Managing GPU Register File
Accepted in IEEE TPDS 2016
Part of the abstract: To support their massively-multithreaded architecture, GPUs use very large register file (RF) which has a capacity higher than even L1 and L2 caches. In total contrast, traditional CPUs use tiny RF and much larger caches to optimize latency. Due to these differences, along with the crucial impact of RF in determining GPU performance, novel and intelligent techniques are required for managing GPU RF.
In this paper, we survey the techniques for designing and managing GPU RF. We discuss techniques related to performance, energy and reliability aspects of RF. We also discuss techniques which propose use of emerging memories (e.g., domain wall memory, STT-RAM, eDRAM) for designing GPU RF. Further, we summarize the trend in RF size in recent NVIDIA GPUs and show contribution of RF in total GPU power consumption.
Accepted in IEEE TPDS 2016
Part of the abstract: To support their massively-multithreaded architecture, GPUs use very large register file (RF) which has a capacity higher than even L1 and L2 caches. In total contrast, traditional CPUs use tiny RF and much larger caches to optimize latency. Due to these differences, along with the crucial impact of RF in determining GPU performance, novel and intelligent techniques are required for managing GPU RF.
In this paper, we survey the techniques for designing and managing GPU RF. We discuss techniques related to performance, energy and reliability aspects of RF. We also discuss techniques which propose use of emerging memories (e.g., domain wall memory, STT-RAM, eDRAM) for designing GPU RF. Further, we summarize the trend in RF size in recent NVIDIA GPUs and show contribution of RF in total GPU power consumption.
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