A question about the Athlons!

[SSP]

Ok, someone asked this question on another forum..

I looked the cache info from WCPUID, and I noticed that it said "Off" under some boxes. Here's a copy of the Cache info:

<< Cache Info. >>

[L1 Instruction TLB]
2-Mbyte/4-Mbyte Pages, fully associative, 8 entries
4-Kbyte Pages, fully associative, 16 entries

[L1 Data TLB]
2-Mbyte/4-Mbyte Pages, 4-way set associative, 8 entries
4-Kbyte Pages, fully associative, 24 entries

[L1 Instruction cache]
64K byte cache size, 2-way set associative, 64 byte line size, 1 line par tag

[L1 Data cache]
64K byte cache size, 2-way set associative, 64 byte line size, 1 line par tag

[L2 Unified cache]
512K byte cache size, 2-way set associative, 64 byte line size, 1 line par tag

[L2 Instruction/Unified TLB]
2-Mbyte/4-Mbyte Pages, Off, 0 entries
4-Kbyte Pages, 4-way set associative, 256 entries

[L2 Data TLB]
2-Mbyte/4-Mbyte Pages, Off, 0 entries
4-Kbyte Pages, 4-way set associative, 256 entries


Anyway, the person who originally posted this question thinks that his L2 cache is off. Anyone know what this is about?

BTW, I noticed on AMD CpuID that there's nothing like &quot;L2 Instruction&quot; and &quot;L2 Data&quot; (it's there for L1, but not for L2).

Here's a screen shot of AMD CpuID.

Thanks for your time. 🙂

 

[SSP]

No one?

 

[xtreme2k]

Athlon's L2 is unified
not split

therefore

[L2 Unified cache]
512K byte cache size, 2-way set associative, 64 byte line size, 1 line par tag

that is all you need to see

 

[Cretin]

Unless he has L2 cache disabled in the BIOS, it's enabled. Get someone else with an identical processor to run the same program and see what appears there.

I can't think of any reason really, I apologize. I don't have a K7 processor, and sadly don't have a whole load of knowledge of it. Is it possible that the K7 treats cache differently and there's some thing to do with &quot;L3&quot; cache?

Sorry if I'm completely off here, but I don't really have a clue what I'm talking about. 🙁

Cretin