A moron question about cpu size.

[philipma1957]

Intel keeps shrinking the transistors in its cpus thus improving them.
(less power use)


65nm to 45nm to 32nm now 22nm .

why is there no talk of an increase in the cpu size.

okay an i7 3770k is about 1.5 in by 1.5 inch or 37.5 mm by 37.5 mm. if you are going to do socket changes every few years. why not make the 14nm size cpu 45 mm by 45 mm or 50 mm by 50 mm. the drop in size from 22nm to 14nm is big change but a layout of

37.5 x 37.5 mm = 1406 mm increased 50 mm x 50 mm = 2500 mm

would allow a more of the 14nm trans.

if you did this the room for truly good integrated graphics would exist. I know it might drive mobo builders nuts, but rumors of welded one piece modules cutting out mobo builders abound.

I have not read anything on a monster cpu/gpu. Any reasons against and/ or for?

 

[tweakboy]

at 14nm their stuck,,,,,, wont go any lower I bet for another few years for sure...

 

[Charles Kozierok]

The primary answer is cost: they want to keep it down.

The secondary answer is portability/mobility/miniaturization.

 

[ShintaiDK]

Bigger size=bigger chance of defects. Plus additional costs.

 

[Ferzerp]

why is there no talk of an increase in the cpu size.

You wouldn't be willing to pay for it. 2x the die area = at least 2x the price

 

[Homeles]

Even if they wanted to bloat the size of a CPU core, what would they put there? There's definitely things they could do to increase performance, but it would be ungodly inefficient.

 

[DominionSeraph]

I have not read anything on a monster cpu/gpu

Xeon E7. 10 cores, 513mm^2, $4500. You can put eight of them in a ~$5000 motherboard.
Sooo... just how much faster do you think eighty 2.4GHz cores are than four 3.4GHz ones for the average consumer?

 

[Ferzerp]

Also, OP is smoking crack claiming a 3770k is 1.5" x 1.5"

 

[ShintaiDK]

Also, OP is smoking crack claiming a 3770k is 1.5" x 1.5"

Isnt that roughly the size of the entire package?

Maybe he needs to see whats under the IHS:

 

[pm]

It's definitely not a dumb question at all... in fact it's very complex question and there are engineers and financial analysts who spend an awful lot of time trying to figure out the "right" size for a CPU. There's five problems with increasing CPU size: power, intra-die process variation, defect density, die-per-wafer, and most fundamentally the "reticle limit".

There's a really great discussion in this thread (from 7 years ago).
http://forums.anandtech.com/messageview.aspx?catid=50&threadid=1613541

CPU's are manufactured on a thin circular sheet of silicon called a wafer - which looks like this. Each of the squares in that sheet is a CPU which people who work in the industry call a "die" (probably from machine shop jargon). Starting with "die per wafer" as the first problem, clearly if you make the individual chips bigger, then you will get fewer of them, but not only are they bigger but any die that touch the edge can't be used (because they are missing a chunk that falls off the side). The bigger each die is, the more space as a percentage that you can't use along the edge of the wafer. But also each individual CPU is bigger and you get fewer of them overall and both of these factors increase manufacturing cost.

Next is defect density. You can imagine defects and being something like a pinch of sand thrown over the wafer. If a grain of this hypothetical sand touches a CPU die, then that CPU won't work and you have to throw it away. So when you throw your pinch of sand on the wafer, you see it scatter randomly all over, and wherever it lands, the CPU won't work. So you can imagine that the bigger each CPU die is, the more of them that won't work. So if you made them all super huge so that there were four of them in a 12" wafer - hypothetically, as we will see, you can't do this - if there were 4 total... then none would work because your grains of sand would touch all 4... unless you got lucky and then you might get one that works. So, the smaller each die is, the more likely it is that it won't have a defect in it and that it will work... and the larger they are, the more you will have to throw away.

Then we start to get into the somewhat more confusing technical reasons. One problem is called intra-die process variation - and I know this one personally because I have worked on several of the largest CPUs that that have ever been made (the Itanium CPU's codenamed: Montecito and Tukwila) and I know very well the problems you have when the die gets enormous. One problem is that they are so big that the electrical characteristics of the transistors vary over the surface of the die. Basically, when you make a CPU die, it sometimes comes out fast and sometimes comes out slow. If it's a fast one, you mark it as being fast and sell it for more money, but if it's a slow one you mark it as slow and sell it for less money. All CPU manufacturing follows this rule... all CPU's come out slightly differently from each other when they are manufactured and some will be fast and some will be slow and some will burn more electricity and some use less and this is called "process variation". When a die gets really big, you can have both slow and fast sections in the same die and this makes the whole die effectively "slow" because you can only run it as fast as the slowest section.

Next you have the "reticle limit". This is a fundamental limit of the lens system that is used to focus the light to make the chip. There's this answer from the old thread mentioned above by Anandtech user Eskimo that explains it:

As someone who used to work for a mask shop i can confirm your limits and it's not entirely due to the process technology but rather the reticle creation technology. Current high end stepper/scanner lithography systems are all 4X reduction systems. This means that the features printed on the reticle are drawn 4 times the size of the intended feature. The standard for reticle substrate sizes is a 6" square quartz plate. 6" is ~150mm in size. At 4x that gives you about a 30mm field size at the wafer level. 4*30mm is 120mm of your total plate and as you get to the edge of the reticle just like the edge of a wafer you suffer from non-uniformity issue. Unfortunately for reticles rather than have die that won't yield at the edge of the wafer the edge of your reticle is the edge of a die and if that side of the die won't print with the same properties as the other side or center you have some major device issues when you go to use it.

Lastly - and it's not one of the main reasons, but it's still important - is power... which goes up the larger a die is. You have to send the clock signal farther which burns more power, there are more transistors in there that use power. Power is higher in larger dies because they are bigger... So those are five good reasons why manufacturers keep CPU die sizes small - and in these days when customers are happy with "good enough" performance, and power is very important and the price becomes one of those most important factors, it's likely that CPU die will continue to shrink into the future.

Patrick Mahoney
Microprocessor Design Engineer
Intel Corp.
* not an Intel spokesperson... just a random engineer that works there *

 

[philipma1957]

It's definitely not a dumb question at all... in fact it's very complex question and there are engineers and financial analysts who spend an awful lot of time trying to figure out the "right" size for a CPU. There's five problems with increasing CPU size: power, intra-die process variation, defect density, die-per-wafer, and most fundamentally the "reticle limit".

There's a really great discussion in this thread (from 7 years ago).
http://forums.anandtech.com/messageview.aspx?catid=50&threadid=1613541

CPU's are manufactured on a thing circular sheet of silicon called a wafer - which looks like this. Each of the squares in that sheet is a CPU which people who work in the industry call a "die" (probably from machine shop jargon). Starting with "die per wafer" as the first problem, clearly if you make the individual chips bigger, then you will get fewer of them, but not only are they bigger but any die that touch the edge can't be used (because they are missing a chunk that falls off the side). The bigger each die is, the more space as a percentage that you can't use along the edge of the wafer. But also each individual CPU is bigger and you get fewer of them overall and both of these factors increase manufacturing cost.

Next is defect density. You can imagine defects and being something like a pinch of sand thrown over the wafer. If a grain of this hypothetical sand touches a CPU die, then that CPU won't work and you have to throw it away. So when you throw your pinch of sand on the wafer, you see it scatter randomly all over, and wherever it lands, the CPU won't work. So you can imagine that the bigger each CPU die is, the more of them that won't work. So if you made them all super huge so that there were four of them in a 12" wafer - hypothetically, as we will see, you can't do this - if there were 4 total... then none would work because your grains of sand would touch all 4... unless you got lucky and then you might get one that works. So, the smaller each die is, the more likely it is that it won't have a defect in it and that it will work... and the larger they are, the more you will have to throw away.

Then we start to get into the somewhat more confusing technical reasons. One problem is called intra-die process variation - and I know this one personally because I have worked on several of the largest CPUs that that have ever been made (the Itanium CPU's codenamed: Montecito and Tukwila) and I know very well the problems you have when the die gets enormous. One problem is that they are so big that the electrical characteristics of the transistors vary over the surface of the die. Basically, when you make a CPU die, it sometimes comes out fast and sometimes comes out slow. If it's a fast one, you mark it as being fast and sell it for more money, but if it's a slow one you mark it as slow and sell it for less money. All CPU manufacturing follows this rule... all CPU's come out slightly differently from each other when they are manufactured and some will be fast and some will be slow and some will burn more electricity and some use less and this is called "process variation". When a die gets really big, you can have both slow and fast sections in the same die and this makes the whole die effectively "slow" because you can only run it as fast as the slowest section.

Next you have the "reticle limit". This is a fundamental limit of the lens system that is used to focus the light to make the chip. There's this answer from the old thread mentioned above by Anandtech user Eskimo that explains it:


Lastly - and it's not one of the main reasons, but it's still important - is power... which goes up the larger a die is. You have to send the clock signal farther which burns more power, there are more transistors in there that use power. Power is higher in larger dies because they are bigger... So those are five good reasons why manufacturers keep CPU die sizes small - and in these days when customers are happy with "good enough" performance, and power is very important and the price becomes one of those most important factors, it's likely that CPU die will continue to shrink into the future.

Patrick Mahoney
Microprocessor Design Engineer
Intel Corp.
* not an Intel spokesperson... just a random engineer that works there *

Thank you. With my background in accounting and computers this answers my question quite nicely. At least in terms that I can understand.

 

[jhu]

It's not the size but how you use it.

 

[itsmydamnation]

another thing, having more transistors doesn't make something faster. in CPU logic you want to have as few transistors as possible to complete the task, thus reducing latency. The off set to this is caches.

It costs a lot of time and power to move data so caching it increases performance. But then there are trade off's in caches, between speed, size, associativity and power.

 

[taltamir]

You wouldn't be willing to pay for it. 2x the die area = at least 2x the price

Cost and price are very different things.
nVidia and AMD are selling GPUs which are much much larger then intel's CPUs at a much lower cost.

Intel's motto is cheap to manufacture, expensive to buy.

Anyways, the problem with making massive die is that their power consumption and heat goes up as well. Although you can compensate with a lower mhz, this is something nvidia has done with massive gargantuan dies which are clocked low. Suitable for GPU and physics processing but not suitable for CPU.

However, its not an insurmountable problem and there is certainly performance to be had by increasing die size... but intel strategy currently focuses on mobile and bringing power consumption ever down to compete with ARM... so its highly unlikely they will do so.

 

[TuxDave]

another thing, having more transistors doesn't make something faster. in CPU logic you want to have as few transistors as possible to complete the task, thus reducing latency. The off set to this is caches.

It costs a lot of time and power to move data so caching it increases performance. But then there are trade off's in caches, between speed, size, associativity and power.

Your statement on transistors is not true in a general sense. You want to accomplish something in the fewest number of logic stages to reduce latency. This is not always accomplished with a solution with the least number of transistors. A carry ripple adder is probably the most efficient in terms of transistor count but it's by far the slowest latency.

 

[itsmydamnation]

Your statement on transistors is not true in a general sense. You want to accomplish something in the fewest number of logic stages to reduce latency. This is not always accomplished with a solution with the least number of transistors. A carry ripple adder is probably the most efficient in terms of transistor count but it's by far the slowest latency.

That there is just a matter of resolution, is an adder a single "task" as i put it. So both are right per say. I was talking more at the level where you are building circuits together to accomplish X (whatever X is).

 

[TuxDave]

That there is just a matter of resolution, is an adder a single "task" as i put it. So both are right per say. I was talking more at the level where you are building circuits together to accomplish X (whatever X is).

The addition of two binary numbers sounds like a "task" to me. The reason why we add transistors to the CPU is to add performance. 32-bit ALUs have more transistors than 16-bit ALUs but they accomplish more tasks faster.

If you're talking about logic reduction and how you can take a large complicated logic equation and reduce it and then get a faster result, that much is true. However when you get to CPU architecture and performance, it's more about algorithm and methodology where more complicated structures that cost MORE transistors will lead to smaller latency for a given task X.

So in the case of the OP, "why not add more transistors to get more performance". If the fabrication cost and power and variation was not an issue, yeah you can add more transistors and get a lot more performance by putting more logic that'll accomplish more tasks at a time.

(btw, I'm not trying to be critical or picky. But "having more transistors doesn't make something faster" isn't right. "having more transistors doesn't necessarily make something faster" is more correct)

 

[Idontcare]

This is an interesting topic. From my perspective it always comes down to money. Even the discussion by pm, extending to Eskimo, is about money.

Process variation is the result of key decision makers in the node's process development cycle electing to invest less money in the development of that node at the accepted expense of then hamstringing the design team with wider tolerances on intra-die variation. It is not a technical limitation, it is simply an ROI decision.

Same with reticle size. The entire industry standardized around a particular maximum reticle size not because of any technical limitations, rather it was purely a financially motivated boundary condition.

Once it became a standard, and the litho equipment and supporting infrastructure (mask shops, etc) grew in place to support the industry then a huge financial barrier came to exist that must be surmounted if the industry were to ever want to change the standard reticle maximum to a larger size. (very similar to what transpires when we transition to a larger wafer diameter 200mm->300mm->450mm).

It just comes down to money.

Likewise with current chip design, xtor density as well as performance/mm^2 density. It is all a conscious trade-off between spending money upfront in R&D versus spending money later with a higher production cost.

Hamstring the design team with a low R&D budget but tell them they can allow the IC to balloon to 315mm^2 and they will get better performance with that 315mm^2 than if you gave them the same low budget but told them they had to shoehorn the design into a 216mm^2 footprint.

But of course in making that decision to spend less upfront on the R&D of the chip's design, resulting in a less efficient design in terms of performance/mm^2, the production cost per chip is going to be markedly higher.

This is where we saw AMD make the right decisions with SOI vs Bulk, and IMO they made the right decisions with their larger die-sized chips in comparison to Intel.

Intel makes a chip design and they automatically get to sell approximately four for every one AMD gets to sell. (talking mainstream x86 chips here) Intel has the volume advantage to justify spending more on the chip's R&D to optimize the diesize upfront and save on lower production costs four times over because they sell four times as many chips.

AMD might end up producing a chip that is larger, costing less to design, but costs more to produce (fewer per wafer)...but because they are selling at a 1:4 volume disadvantage the aggregate excess cost-of-production for those chips won't out-weigh the R&D savings that were realized when they elected upfront to spend less on the chip's R&D in the first place.

And of course Moore's Law captures one aspect of this as Moore's Law was always about the rate of reduction in costs per component that constitutes the IC.

 

[tweakboy]

Xeon E7. 10 cores, 513mm^2, $4500. You can put eight of them in a ~$5000 motherboard.
Sooo... just how much faster do you think eighty 2.4GHz cores are than four 3.4GHz ones for the average consumer?

LOL funny you are...... lmao ..........................

omg 5k motherboard wow, LOL

Man if 10 cores are 4500 dollars. Then wtf is Ivy Bridge E going to cost, since it will have 6 to 12 cores......... I wont pay more then 600 for a CPU. Not top tier but the middle one. sorta like 3930k but 4870k or whatever the Ivy Bridge E is gonna be called.

 

[philipma1957]

This is an interesting topic. From my perspective it always comes down to money. Even the discussion by pm, extending to Eskimo, is about money.

Process variation is the result of key decision makers in the node's process development cycle electing to invest less money in the development of that node at the accepted expense of then hamstringing the design team with wider tolerances on intra-die variation. It is not a technical limitation, it is simply an ROI decision.

Same with reticle size. The entire industry standardized around a particular maximum reticle size not because of any technical limitations, rather it was purely a financially motivated boundary condition.

Once it became a standard, and the litho equipment and supporting infrastructure (mask shops, etc) grew in place to support the industry then a huge financial barrier came to exist that must be surmounted if the industry were to ever want to change the standard reticle maximum to a larger size. (very similar to what transpires when we transition to a larger wafer diameter 200mm->300mm->450mm).

It just comes down to money.

Likewise with current chip design, xtor density as well as performance/mm^2 density. It is all a conscious trade-off between spending money upfront in R&D versus spending money later with a higher production cost.

Hamstring the design team with a low R&D budget but tell them they can allow the IC to balloon to 315mm^2 and they will get better performance with that 315mm^2 than if you gave them the same low budget but told them they had to shoehorn the design into a 216mm^2 footprint.

But of course in making that decision to spend less upfront on the R&D of the chip's design, resulting in a less efficient design in terms of performance/mm^2, the production cost per chip is going to be markedly higher.

This is where we saw AMD make the right decisions with SOI vs Bulk, and IMO they made the right decisions with their larger die-sized chips in comparison to Intel.

Intel makes a chip design and they automatically get to sell approximately four for every one AMD gets to sell. (talking mainstream x86 chips here) Intel has the volume advantage to justify spending more on the chip's R&D to optimize the diesize upfront and save on lower production costs four times over because they sell four times as many chips.

AMD might end up producing a chip that is larger, costing less to design, but costs more to produce (fewer per wafer)...but because they are selling at a 1:4 volume disadvantage the aggregate excess cost-of-production for those chips won't out-weigh the R&D savings that were realized when they elected upfront to spend less on the chip's R&D in the first place.

And of course Moore's Law captures one aspect of this as Moore's Law was always about the rate of reduction in costs per component that constitutes the IC.

So from the background of cost accounting. It would simply cost a huge amount of money to build all new fabrication equipment plus time and money spent on designing it. The risk of that cash invested outweighs the possible gain of selling a monster cpu/gpu.

I kind of thought that this was the biggest stopping point. It is interesting to get some good info on the subject thanks.

 

[ShintaiDK]

Cost and price are very different things.
nVidia and AMD are selling GPUs which are much much larger then intel's CPUs at a much lower cost.

Intel's motto is cheap to manufacture, expensive to buy.

Dont mix GPUs and CPUs.

GPUs contain basicly large amount of "copy/paste" logic. And you can easily disable one without sacrificing the product too much. If Intel produces a quadcore with a defect core. it goes to the trashbin. For CPUs you more or less only got spare L2 cell blocks that you can disable/enable with defects.

In short, its much easier to produce a large GPU than a large CPU in yield terms.

 

[Ferzerp]

They also aren't selling them at a "much lower" price. The're also on a 28nm process which is about 1.6 times less dense, meaning that an IB 160mm^2 die is similar to a 256 mm^2 die @ 28nm which is nearing the size of the bigger 600 series from nvidia which is at 294 mm^2. A 680 costs *much* more than a 3770k (and I imagine so, even if we remove the non GPU BOM)
This is just fud which pretends that all die areas are equal regardless of process, and all designs are the same. I see this happen a lot here..

 

[DominionSeraph]

They also aren't selling them at a "much lower" price. The're also on a 28nm process which is about 1.6 times less dense, meaning that an IB 160mm^2 die is similar to a 256 mm^2 die @ 28nm which is nearing the size of the bigger 600 series from nvidia which is at 294 mm^2. A 680 costs *much* more than a 3770k (and I imagine so, even if we remove the non GPU BOM)
This is just fud which pretends that all die areas are equal regardless of process, and all designs are the same. I see this happen a lot here..

You do know the GK104 was supposed to be the successor to the GF114, right?
You do know that the GTX 660 Ti uses the same die as the GTX 680, right?

 

[Ferzerp]

You do know that the GTX 660 Ti uses the same die as the GTX 680, right?

You think the 3770k is the only model using the same die?

 

[Idontcare]

This is just fud which pretends that all die areas are equal regardless of process, and all designs are the same. I see this happen a lot here..

Its not fud, it is just an honest misunderstanding (justifiable ignorance owing to a lack of experience)

As one professional to another I urge caution in interpreting comments from what are essentially non-industry folks grappling with their misunderstanding of something that us industry folks live and breath as second-nature. Not everyone here is going to know what project management actually entails, what R&D efficiency means in practice, what die-harvesting does to one's cost model and so forth.

Patience and a measured response are what's called for, resist the urge to assume malice (fud) is afoot when one can just as easily recognize it is a just a perception and awareness issue at the root.