- Feb 2, 2008
superstition said:What I'd like to know is when the arsenide tech is going to replace silicon. It operates in the terahertz range.
December 2014 said:Transistors made from gallium arsenide nanowires shatter previous speed records, demonstrating that the materials could provide an alternative to silicon
Nanowires offer a way around the wafer cost problem, because they should use less material.
nanowires like to grow vertically, out of the plane of the substrate, making it tricky to pattern electrical contacts on top, says Xiuling Li, an electrical engineer at the University of Illinois, Urbana-Champaign. So when one of Lis students let her know that some of the GaAs nanowires in their batches had grown horizontally along the surface of a wafer, Li saw it as an opportunity
Li has used the nanowire arrays to make a type of high-performance transistor similar to those found in radar equipment and cell-phones. Each 10-µm-wide transistor contains about 30 nanowires, along with three electrodes. A top electrode called a gate applies a voltage across the device to switch the nanowires between conducting, or on, and insulating, or off, states. In the on state, charges flow between source and drain electrodes. The transistors have blistering switching speeds, turning on and off 75 billion times a second, or at 75 gigahertz. The previous record for planar nanowire transistors was 1.8 GHz.
She wants to adapt the method to indium arsenide, another III/V material. The mobility of indium arsenide is three times higher than gallium arsenide, so if I can make it work, I think we can get to terahertz speeds, she says.
March 2015 said:New process could make gallium arsenide cheaper for computer chips, solar cells
it can cost about $5,000 to make a wafer of gallium arsenide 8 inches in diameter, versus $5 for a silicon wafer, according to Aneesh Nainani, who teaches semiconductor manufacturing at Stanford.
The new Stanford process seeks to lessen this thousand-to-one cost differential by reusing that $5,000 wafer.
Today the working electronic circuits in a gallium arsenide device are grown on top of this wafer. Manufacturers make this circuitry layer by flowing gaseous gallium arsenide and other materials across the wafer surface. This material condenses into thin layer of circuitry atop the wafer. In this scenario, the wafer is only a backing. The thin layer of circuitry on top of this costly platter contains all of the electronics.
To make the wafer reusable the Stanford process would add several steps to the manufacturing process. The researchers demonstrated the technique in their experiments.
First they covered the precious wafer with a layer of disposable material. Then they used standard processes of gas deposition to form a gallium arsenide circuit layer on top of the disposable layer. Next, using a laser, they vaporized the disposable layer and lifted off the circuitry layer like flapjack on a greased griddle. They mounted this thin circuitry layer on a more solid backing and cleaned the costly gallium arsenide wafer to make the next batch of circuits.
Nainani estimates that this reuse could create gallium arsenide devices that would be 50 to 100 times more expensive than silicon circuits still a big differential but much less than what exists today.
It all boils down to economies of scale, Clemens said.
"Once it becomes possible to make gallium arsenide more cost-effectively, other people will jump in to improve other parts of the process,'' Clemens said. "And with each advance, more uses will open up..."
A bit droll that computer gaming enthusiasts may have to thank environmentalists for a major advance in computing tech, powering their GPUs and CPUs. This is because solar energy in particular is an area where this arsenide nanowire tech shines. However, 75 GHz to terahertz speeds isn't exactly slouching when compared with silicon!October 2015 said:A GaAs nanowire array solar cell with an independently verified solar energy conversion efficiency of 15.3% and open-circuit voltage of 0.906 V under AM1.5g solar illumination at 1-sun intensity has been fabricated. This is the highest published efficiency for nanowire array solar cells and is twice the prior record for GaAs nanowire array solar cells.
So silicon may not die so soon, even if arsenide nanowire tech is made commercially viable.June 2015 said:IBM Integrates III-V Nanowires on Silicon
The team has developed a method to build nanowires and multi-gate transistors, from III-V compound semiconductors on top of silicon-on-insulator (SOI) wafers.
The techniques being reported by IBM could be in demand at the 7nm or 5nm nodes.
The method is called template-assisted selective epitaxy (TASE) and the combination of semiconductor types is significant because III-V compound semiconductors have intrinsically higher electron mobility than siliconwhich is related to switching speed and performancebut the silicon manufacturing ecosystem is more mature and allows economies of scale, such as manufacturing on 300mm diameter wafers in large wafer fabs. IBM claims to have made progress in trying to achieve this integration of compound and silicon processing.
Numerous previous attempts to address the crystal lattice mismatch between silicon as the carrier wafer and the III-V materials, such as compounds of indium, gallium and arsenide, are referenced in the paper but only as being partially successful. They have been accompanied by either the presence of significant crystal defects or have required extensive surface preparation and multi-step processing and therefore are costly, or have only been applicable to the creation of vertical structures.
Now, the IBM team claims to have made many of the lateral structures required to allow integration of compound semiconductors with silicon processing as an evolution of the FinFET. This single crystal nanostructures include nanowires, nanostructures containing constrictions, and cross-junctions, as well as 3D stacked nanowires.
The TASE technique uses lithography and reactive ion etching applied to an SOI wafer to predefine the structures required in a thin layer of silicon on top of the silicon-oxide insulator. The wafer then receives a 30nm-thick silicon oxide blanket, creating nanostructure templates defined in silicon and silicon oxide. These template structures are subsequently etched back to expose a silicon crystal plane that is well matched to the orientation of a particular compound semiconductor. Such a semiconductor is then deposited by metal-organic chemical vapor deposition (MOCVD). The first layers of compound semiconductor then act as the seed that allows much larger defect-free monocrystalline compound semiconductors to be grown, effectively filling in the oxide template with III-V epitaxy.
To demonstrate the technique, the research team has reported results for indium arsenide (InAs) nanowires measuring 95nm wide by 23nm thick, for Hall Effect structures measuring 50 microns wide by 20nm thick. InAs multigate FETs measuring 25nm wide and 23nm thick with an aluminum oxide gate over hafnium oxide high-k dielectric over titanium nitride were also fabricated and measured and found to perform well.
"What sets this work apart from other methods is that the compound semiconductor does not contain detrimental defects, and that the process is fully compatible with current chip fabrication technology," says Heinz Schmid.
A further advantage of the use of III-V compound semiconductors as the active device material rather than silicon is that, it also supports the creation of optoelectronic devices. These could be used to create on-chip light emitters and receivers, which have been touted for the on-chip transmission of high-speed signals.
Two-Step Growth Method for InGaAs Nanowires for High-performance Electronic Devices