a basic vhdl question

[Zhenmeister]

i have an simple assignment in vhdl that says the following:
"write a vhdl program for an XOR gate w/2 inputs and 1 output using one simple signal assignment statement"

i am not sure how to interpret the condition "one simple signal assignment statement".
would this do it?


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ENTITY xor IS

PORT (w0, w1 :IN STD_LOGIC;
f 😱UT STD_LOGIC);

END xor;

ARCHITECTURE Behavior OF xor IS
BEGIN
PROCESS (w0, w1)
BEGIN

IF w0 = '0' THEN
f<=w1;
ELSE
f<=w1';
END IF;
END PROCESS;
END Behavior;


Any help would be appreciated