8KB page size on IMFT new 25nm flash?

[IntelUser2000]

http://www.electroiq.com/index/disp...-news/2010/february/analyst-take__inside.html

From the video, the presenter explains at 5:50-5:59 pretty much conclusively that while they could have gone with 3-bit per cell NAND at 34nm, they found 25nm better on reliability and density characteristics and will take that road instead.

Whether the 3BPC 34nm went to silicon or not, that part seems to be true:
http://www.eetimes.com/showArticle.jhtml?articleID=219200014&pgno=2

They had the die size numbers back then, wafers could have existed. But now its scrapped for future development and more advanced process nodes.

 

[mutz]

yay! thanks, just came across it, there's lot's of information to go through.

the main difficulty with going x3 and x4 BPC is the voltage adjustments which raises the BER, there seems to be a slow down too adding more BPC's.
in order to set the bit state they use different voltages, i.e - 1.0 would go for a certain cell and 1.5 would go to another,

You have to do it much slower (to the point of more than 1 second per page of 48 sectors), the page size and block size becomes much larger, and a cell becomes worn out way earlier than before. Instead of having 1.25V safety margin, you now have only 0.625V. The latest data is that you can only program / erase a cell 500 cycles (vs 100k cycles in SLC and 5k cycles in 2 bit per cell MLC) without garbage collection.

ECC also needs to be much stronger. From the 6 bits back in SLC days to 12 bits in MLC to now 24-42 bits in 43nm 3LC, and 122 bits in 32nm 3LC already in the FAB. Some chips are the same (i.e Toshiba's 43 and 32nm last gen 3LC) and is only the operation mode that determines whether it was SLC/MLC/3LC, but to meet performance target (i.e. SDHC speed class 4), the next gen chips for 3LC will be dedicated, custom design that cannot be SLC or 2LC.

back again, that says it all,
3BPC seems to be the step when shrinking the nodes further won't be possible anymore, as further going into that crossroad, memory companies should have to figure bringing 3BPC into 2 bit MLC's speed and endurance.
Micron has a video showing they're aim at producing 100K P/E cycle MLC which could replace SLC in certain applications offering higher density & reliability for lower costs so maybe one of the hurdles is off.
OT,
customers complain over these speeds and the others, it all seems so easy after the product is made, while engineers over these companies actually face huge challenges...
this is kind of absurd

,
like a father working all day long to sustain children who don't appreciate it.