8KB page size on IMFT new 25nm flash?

[mutz]

http://www.anandtech.com/show/2928
and no one (neither anand) has even addressed it through the comments

write amplification.. any idea's?

E:
could be leveled by caching though.

 

[Emulex]

1-bit > 2-bit

 

[mutz]

sorry, not following..

 

[Mark R]

8 kB page size could be tricky to work with. This would mean 'read-modify-write' for 4 kB pages. Meaning reduced speed and increased write amplification.

Probably the easiest way to get around this would be to increase the amount of overprovisioning, in order to maximize write coalescing and drop WA far as possible.

 

[mutz]

maybe intel would cache 8KB chunks of data at random write (sorry) patterns and then flowing it to the NAND, or more complicated, let the controller decide when an 8KB data packet can be released to the NAND by adding piece by piece into it and algorithmic leveling the cache blocks to minimize write amplification or lost of nand space to 00 data.

a 4KB packet would be cached till it fills up an 8kB buffer then be written to the memory cells, smaller ones would periodically add up.

 

[FishAk]

OK, Emulex, maybe I'm just daft


“1-bit > 2-bit “


Can you explain for a simpleton?

 

[Emulex]

hmm i think i got cut off
1-bit -> slc
2-bit -> mlc
3-bit -> something new mlc

we'll see trickles of 3-bit cheap ssd from this - probably pretty crappy since any time you want to change 1 bit you'll have to flip 3 bits.

less reliability - probably faster read speeds, and higher density. Maybe not intel but a 3rd party buyer of micron flash

 

[mutz]

the 2 bit MLC is supposed to be for enterprise SSD..
faster then the 3-bit and more reliable.

they are designing some 100k write cycle MLC currently.

 

[Mark R]

I do wonder whether 3-bit MLC would be suitable for SSDs. I suspect the cycle life and data integrity will be somewhat compromised compared to 2-bit, as well as write speed being much slower - and it would be a false economy to use it for heavy workloads.

I suspect it'll be reserved for USB sticks, low-end memory cards, and the like, which are very light duty compared to SSDs - and where price is the primary selling point, not quality.

The thing about flash memory is that it is a trade off between: high density (smaller cells and more bits per cell) and high integrity (better cycle life and better data preservation). You have to choose one that is more important than the other. Smaller cells are less reliable, have shorter cycle life and shorter data retention time. Bigger cells are more reliable and have longer cycle life. The manufacturers are now eking out tweaks to try and improve both at the same time - but it's tough work.

 

[mutz]

if i'm not mistaking, smaller cells vs bigger cells goes hand in hand with the process technology, i.e 50nm, 34nm, 25 etc.
single bit SLC is far more resilient then MLC's and tweaking the instruments to suffer harder and longer abuse comes with more appropriate materials and better circuit design.
by storage search, MLC goes between 3-7 bits per cell as the more bits there are, lesser is they're quality.
assuming in order to write a single cell would require a larger portion of the storage capacity i.e 3 bit vs 2, it's write cycle & endurance would decrease.
have a look at the brief video here by micron which explains some of it's marketing strategy in regards to SLC, MLC and 3BPC:
http://www.micronblogs.com/2009/08/slc-mlc-3-bit-mlc-nand%E2%80%94what%E2%80%99s-the-difference/

micron has some outstanding technical notes and papers, very much worth reading!

http://www.anandtech.com/show/2928

Last year IMFT announced plans to deliver a 3-bit-per-cell 34nm MLC NAND flash. Today's announcement pretty much negates the need to bring those devices to market. Although at some point we'll probably see 3-bit-per-cell at 25nm. At this point 3-bit-per-cell MLC flash is only suitable for cheaper or low cycle devices like USB sticks. In a SSD the performance and reliability tradeoffs just aren't worth it.

this is right then 2BPC goes for SSD's and 3BPC MLC for USB devices and hybrid SSD's with 2 bit MLC or SLC as primary NAND.

Micron 30K MLC 300K SLC:
http://www.techspot.com/news/36631-microns-enterprise-mlc-nand-boosts-endurance-by-600.html

 

[VirtualLarry]

http://forums.anandtech.com/showthread.php?t=2079889

 

[IntelCeleron]

if i'm not mistaking, smaller cells vs bigger cells goes hand in hand with the process technology, i.e 50nm, 34nm, 25 etc.
single bit SLC is far more resilient then MLC's and tweaking the instruments to suffer harder and longer abuse comes with more appropriate materials and better circuit design.
by storage search, MLC goes between 3-7 bits per cell as the more bits there are, lesser is they're quality.
assuming in order to write a single cell would require a larger portion of the storage capacity i.e 3 bit vs 2, it's write cycle & endurance would decrease.
have a look at the brief video here by micron which explains some of it's marketing strategy in regards to SLC, MLC and 3BPC:
http://www.micronblogs.com/2009/08/slc-mlc-3-bit-mlc-nand—what’s-the-difference/

micron has some outstanding technical notes and papers, very much worth reading!

http://www.anandtech.com/show/2928


this is right then 2BPC goes for SSD's and 3BPC MLC for USB devices and hybrid SSD's with 2 bit MLC or SLC as primary NAND.

Micron 30K MLC 300K SLC:
http://www.techspot.com/news/36631-microns-enterprise-mlc-nand-boosts-endurance-by-600.html

That explains this:

Around the same time we’ll see a refresh in the X25-E space with 34nm MLC flash. Yep, you read that right. Intel appears to be going after the enterprise market with MLC flash. Which means that Intel’s third generation SSD controller is going to have write amplification under control in a serious way.

 

[mutz]

http://forums.anandtech.com/showthread.php?t=2079889

lol, 3.3 years out of 10 ! and 10 writes for 3 BPC USB flash WTH D:
that sounds impossible, who would manufacture NAND going 10 write cycle ? i can't accept that.

That explains this:

interesting datasheet on ONFI standards from legacy NAND to 2.1 with relation to page sizes latencies:
http://onfi.org/wp-content/uploads/2009/02/onfi2_1webcast.pdf

the first part of the document atleast (the rest is a bit more complex )

 

[IntelUser2000]

IMFT wanted 3-bit per cell MLC at 34nm node, but since the 25nm node was too close to its release by the time the 3-bit MLC was ready, they cancelled the 3-bit project and went to 2-bit 25nm.

That's probably the reason why the early roadmaps had "Postville refresh" on the same 34nm while the only thing we see now is "Taylorsville" on 25nm.

I read the reason for bigger page sizes is because the speeds to access the array slows down and in order to scale performance larger page sizes are necessary.

BTW, I think the lifecycle for the 25nm MLC cells are 5K. That's probably an average figure I'm assuming. They can use higher quality chips that have increased lifespan. I think the X25-E is using 200K cells.

 

[Emulex]

dude i've got a sandisk 2GB sdhc in a panasonic camera. it uses fat or something ancient since its *bsd based camera o/s. anyways it's been recording on motion at 640x240 for the last 3 years in rotary fifo so i'd suspect insane amounts of writes. i took it out recently for audit and did a chkdsk read and found no bad sectors. i figured (hence audit) the module would need replacement. very impressed.

hmm i need to ask intel for engineering samples (Raid-0!) of new x25-E if you time it just right they don't want them back. they use Flash Back Write cache (super-capacitor) like the hp smartarray controller sorta - so this enhances the heck out of everything. intel will safely use write-back cache from what i've read (non-nda stuff).

 

[Idontcare]

lol, 3.3 years out of 10 ! and 10 writes for 3 BPC USB flash WTH D:
that sounds impossible, who would manufacture NAND going 10 write cycle ? i can't accept that.

Consider the source. Those guys have a vested interest in painting a picture of the world being on the cusp of needing their data recovery services.

This kind of preliminary, low sample count, data is needed to make TAM (Total Available Market) projections with ridiculously large (but never included with the figures) error bars on the upper limits of the estimates.

TAM projections are needed if you are scouting out venture capital or are shopping yourselves around to be bought out.

 

[=Wendy=]

Good quality 34nm NAND is more likely 4k - 6k cycles.
25nm NAND is more likely closer to 3k cycles for good quality stuff, but could be as low as 1.5k cycles.
Basically it's down to pure physics and the materials used to construct the NAND.

 

[Voo]

Good quality 34nm NAND is more likely 4k - 6k cycles.
25nm NAND is more likely closer to 3k cycles for good quality stuff, but could be as low as 1.5k cycles.
Basically it's down to pure physics and the materials used to construct the NAND.

So far I haven't seen any believeable, reliable experiments with a large enough sample on that, everyone throws around numbers but nobody can back them up :/

Would be great if anyone had a link/paper on that at hand, but the important part is "believeable", a sample of one without any given error rate is just meaningless.

 

[Idontcare]

Voo this recent master's thesis on the topic may add some value to your understanding what endurance limits mean and how they are determined.

http://www.cs.virginia.edu/~vm9u/files/Master's%20Thesis.pdf

 

[Voo]

Voo this recent master's thesis on the topic may add some value to your understanding what endurance limits mean and how they are determined.

http://www.cs.virginia.edu/~vm9u/files/Master's%20Thesis.pdf

Thanks for digging that up.

Just skimmed over it and it looks promising. Got to read at least some chapters in detail this weekend or when I've got some spare time, but the testing methodology makes sense (and different than what I thought.. "just write to it and look when it dies" )

 

[mutz]

by storage search, MLC goes between 3-7 bits per cell as the more bits there are, lesser is they're quality.

this is wrong, couldn't find the article at that site, though there seems to be even 4BPC MLC's delivered by sandisk,
no way intel's 3BPC MLC goes after 10 write cycles,
or rather these specific chips are faulty.
they are said to deliver 3BPC already since Q4 2009.
http://www.dailytech.com/Intel+Micron+Joint+Venture+Rolls+Out+32Gb+3bpc+NAND/article15954.htm

everyone throws around numbers but nobody can back them up

you can also view this comment regarding 3BPC and MLC cycles,
the numbers are generally 10K as for MLC and 100K for SLC with the exception above researched 30K and 300K by Micron, as well there should be much more resilient cells for maybe heavy enterprise or army usage going way up (2 million cycles).

should it matter really if it's 10k or 5.5 lasting 40 years or even 5 when you have 3 to 5 years warranty?
anyhow:

SLC (1 bit per cell) vs MLC (2 bit per cell) has a 2x capacity improvement for marginally increased cost. In 3 bit per cell (aka 3LC) there will be another 50% increase in capacity for literally no die size increase.

It is done by charging/discharging the floating gate in the cell to a precise voltage/charge (write) so that it can be detected later (read). It is easy if you just need to charge/discharge between on and off, harder if you want to do between 0, 1.25, 2.5, 5V, and very hard if you want 0, 0.625, 1.25, 1.925, etc... because there aren't much margin of error.

You have to do it much slower (to the point of more than 1 second per page of 48 sectors), the page size and block size becomes much larger, and a cell becomes worn out way earlier than before. Instead of having 1.25V safety margin, you now have only 0.625V. The latest data is that you can only program / erase a cell 500 cycles (vs 100k cycles in SLC and 5k cycles in 2 bit per cell MLC) without garbage collection.

ECC also needs to be much stronger. From the 6 bits back in SLC days to 12 bits in MLC to now 24-42 bits in 43nm 3LC, and 122 bits in 32nm 3LC already in the FAB. Some chips are the same (i.e Toshiba's 43 and 32nm last gen 3LC) and is only the operation mode that determines whether it was SLC/MLC/3LC, but to meet performance target (i.e. SDHC speed class 4), the next gen chips for 3LC will be dedicated, custom design that cannot be SLC or 2LC.

That's all I can say in the public domain (since every one that uses Toshiba memory knows them already). Anything beyond this is proprietary.

PandaBear - a SanDisk engineer

 

[IntelUser2000]

IMFT never delivered 3BPC NAND flash. That DT article was just an announcement. I'll find an article that explains that in little more detail if anyone wants.

 

[mutz]

they were talking about intel flash through VirtualLarry's link for U.S.B usage lasting 10 cycles,
put aside the credibility and interest of the writers, still doubtfully it is a 2 bit NAND.
though indeed, never heard of Intel or Micron actually producing any 3BPC MLC,
they are saying it is supposed with the 25nm node.

 

[mutz]

that thesis is quite long (and would take about a month? to read with all the references) so
here's something for the meanwhile:
showing few MLC's and SLC's from different manufacturers, they seem to hold on to they're specs, the error rate seems ~ fine..? till 10,000k or a bit shy when it leaps up, maybe it depends on the ECC algorithms implemented and number of bytes in the OOB portion of the disk.
the letters stand for different manufacturers (A,B,C,D,E), the numbers go for capacity (2,4,8,32,64) and the ending 1 & 2 goes for different portions of the same chip, different dies or planes:

http://nvsl.ucsd.edu/papers/TR-CSE-CS2009-0946-FTest.pdf
at p.7.

Figures 6 and 7 show the error rate for each chip. The difference between SLC and MLC is stark. MLC devices show
significant error rates from the very beginning. For most of the MLC models, the error rate increases sharply shortly after
their rated lifetime, and some start to increase sharply even earlier. SLC devices, by contrast, show almost zero errors until
they reach their rated lifetime and maintain reasonably low rates for up to six times their rated lifetime.
It is important to realize that these data do not include any effects on the “shelf life” of the data stored in these devices.
However, not all applications require the 10 year data retention time that manufacturers aim to provide.

 

[mutz]

p.s - look at the C-MLC64-2 drive, when it reaches about 7,000 P/E cycles, it seems to have some (1e^^-5)/2 BER or ~ an error per 200K write bits (is that right?) which seems a lot -
that's an error every 25kB of data that should be where ECC comes into play.

the Y axis goes for the error rate,
here, differences between two chips on the same drive can be seen,
same as with processors, every die is slightly different.