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800 Million Transistors go Missing

The 2B number was always suspect since AMD disclosed a BD module (including L2) contained 213M transistors. 8MB of L3 is about ~470M (including ECC, tags). This adds up to about 1.3B transistors but doesn't include the memory controller, I/O and crossbar. Those tend to use up alot of area but relatively little transistors. Yeah I don't believe the 1.2B number either.... It's probably closer to 1.4B or so would be my guess.
 
Looks like new revision really optimized design 😀

And lol what a company to miscount transistors on their own chip by only 40% margin.
 
I still can't figure out how the hell they give reviewers the wrong number to begin with, much less take 3 months to realize the error and correct it.

The 1.2B count makes a whole lot more sense, though.
 
I don't know if this is a good thing, considering how much power it consumes with now only "1.2B" transistors.

I'd rather not ever know how much power a 2B transistor FX processor at .32nm would consume (300W+?).
 
zlejedi said:
Looks like new revision really optimized design 😀

And lol what a company to miscount transistors on their own chip by only 40% margin.
Click to expand...

Hilarious situation when they don't even know wtf they are making.

A total joke, everyone involved with the BD development in the AMD CPU division should be fired if this actually occurred (and not just a lame PR spin).
 
I wouldn't mind if they have mistaken the figure for about 100 million but for 800 million? I'm skeptical. :hmm:
 
The design/marketing teams for Bullderper should be fired.

It's not acceptable to "revise" downwards the transistor count by 40% after such a long time.
 
So it is 20% more transistors than a 2600k, but has a 50% bigger die. Which means that 20% of the die is wasted space, and/or each transistor takes up 20% more space. Either way it is an epic fail.
 
sm625 said:
So it is 20% more transistors than a 2600k, but has a 50% bigger die. Which means that 20% of the die is wasted space, and/or each transistor takes up 20% more space. Either way it is an epic fail.
Click to expand...

Yeah but it also has twice as many cores!
 
This is just comical.

You guys do realize why AMD felt compelled to report the originally higher number, right?

They made such a big deal at GloFo that their decision to go gate-first was superior to Intel's because it was going to give them superior scaling and superior transistor density.

That didn't happen, clearly. And now that the honeymoon between AMD and GloFo is over, with AMD cancelling their 28nm brazos shrink, AMD now no longer feels compelled to be the PR mouthpiece that is/was vouching for GloFo's previous technology claims.

The reality is the xtor density did not drastically improve, they made a performance trade-off to go gate-first in hopes of nailing a cost benefit in yields and die-size and they failed on both accounts.

It is funny still though that even the 1.2B number is BS as pointed out above, it falls short when accounting for the stuff we know to be there (L3$) without accounting for the other stuff we know is present (IMC, IO, etc).

AMD, please stop the facepalm train, just cry uncle and stop making fools of yourselves 🙁
 
sm625 said:
So it is 20% more transistors than a 2600k, but has a 50% bigger die. Which means that 20% of the die is wasted space, and/or each transistor takes up 20% more space. Either way it is an epic fail.
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Doesn't the cache take up more space than components? 😛 And bulldozer has a crapton of cache?
 
antisocialmunky said:
Doesn't the cache take up more space than components? 😛 And bulldozer has a crapton of cache?
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Cache is usually more dense than logic.

And the GPU logic is more dense than the CPU logic, that is why Llano's computed density (if we can believe the xtor counts for it anymore) is so high.

If you only need the circuits to clock at 600-800MHz then you can get away with making the circuits much much smaller than if you need them to clock at 3-4GHz.

That is also part of the motivation for making the larger L3$ clock slower than the core logic, they can make the L3$ much denser than the logic if they intend to clock it slower than the logic. This is also the reason why L1$ tends to be quite big, not dense, because they need it to clock fast and with low latency.
 
Well it takes less space up to a point but then you have a crap ton of cache which takes up space, you have 8 cores/4 modules but then you tack on 8 MB of L2 and 8MB of L3.
 
I'm still amazed by intel's few year old accomplishment of cramming 12MB of L2 on the yorkfields (granted it was a 2 die design, but still).
 
sm625 said:
So it is 20% more transistors than a 2600k, but has a 50% bigger die. Which means that 20% of the die is wasted space, and/or each transistor takes up 20% more space. Either way it is an epic fail.
Click to expand...

Isn't the bulldozer transistor density lower than in previous arches to allow higher clock speeds?

edit: I meant to say "lower than it should have been if the bulldozer arch didn't go for moar megahertz"; obviously it can't be lower that previous arches that were build on bigger, older processes...
 
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According to Anand's writeup, GloFo's 32nm process takes both the top and bottom spots for 32nm xtor density. Or am I reading this chart incorrectly?
 
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