Perhaps my wording didn't make it clear, but under what situations would the hardware want to do that? The larger cache improves performance and reduces the amount of time that the CPU needs to run because it doesn't need to wait on as many memory accesses. If that weren't the case, we wouldn't see a 15% performance improvement despite a ~5% reduction in clock speed.
Really the only time you'd want to turn it off is if the system is idle at which means that the cores don't need additional power to boost either. Otherwise as long as the system is operating, you'd always want to have the additional cache active because it ultimately saves power.
You don't always need such a massive cache. Many programs fit just fine inside Zen's 32 MB of existing L3 cache and won't see any uplift with the extra cache. If the extra cache isn't being used, it doesn't make sense to waste power by continually refreshing it.
My original point was that AMD has kept the same TDP for the 5800X3D as it had for the 5800X. Because the cache requires power, it means that there's less that can be supplied to the remainder of the chip so the clock speeds naturally decrease. Of course, if you don't care about that and are willing to bypass those limits, it's entirely possible that you can still achieve the same clock speeds on a 5800X3D as you could on a 5800X assuming that the limits aren't also due to binning changes. Even if there were binning changes that just means a greater variability in silicon quality and that some parts could still reach those clocks, but there's no guarantee.
The base clocks will be set based upon max core utilization, meaning the full L3 cache is engaged. Potentially, in real world clocks, if the V-cache is powered off then you would still see the same base clocks as the standard 5800x, assuming all else being equal. I'm honestly not really sure that thermals will be an issue as the cache doesn't get that hot and the only area where there is cache sits above only cache so it shouldn't get as hot as within the FPU units for instance.
The rest of the top layer that sits above the rest of the base CPU is substrate designed for low thermal resistance. The amount of substrate above the CPU logic/registers is the same in the V-cache SKUs as it is in the regular SKUs because they have the same total thickness. The stability substrate in the V-cache SKUs should be as good, if not better, thermally conducting than the substrate in the regular SKUs. The question is at the interface, how much thermal resistance appears there? I don't know, but it should be relatively quite thin and using low thermal resistive bonding so I wouldn't think it would add all that much, but I don't really know.
Does the L3 cache clock at the same speed as the cores in Zen 3? Anyone know?