64bit CPUs +Opteron

[jema]

Wondering if anyone can explain why 64bit CPUs (Ive checked IBM, Sun, SGI & Intel) dont go above 1GHz?

Follow-up Q Nr1: Where will the Opteron end up in all this? If it is some sort of technical speed limit will it then run the core at different speeds or is it one speed and some sort of code conversation for 32bit?

Follow-up Q Nr2: Is there any point in running 64bits for home/office use? What I've been told is that we're not really using the 32bits we got to the max.

 

[Soulkeeper]

cause they don't need to
MHZ isn't everything i'm sure there are some good articles on the internals of cpu architecture and design
lets see theres pipeline stages ipc's...........

 

[BuddyAtBzboyz]

Think of it this way at 64 bit they are sending 2x as much information per clock. Kinda like ddr for the cpu. So at 1ghz its more like a 2ghz processor when you are doing something that can take advantage of the 64bits. Very simplistic explanation but I hope it helps.

 

[AndyHui]

Originally posted by: BuddyAtBzboyz
Think of it this way at 64 bit they are sending 2x as much information per clock. Kinda like ddr for the cpu. So at 1ghz its more like a 2ghz processor when you are doing something that can take advantage of the 64bits. Very simplistic explanation but I hope it helps.

It is also an incorrect explanation.

Please read the FAQ: The Myths and Realities of 64-bit Computing

 

[jema]

Works for me, thanx.

Tech docs wouldnt do me much good, Ive sneaked peaks at some of them in the past and I get FA.

The G4s are 32bit right? Apple pushing that "MHz isnt everything" pretty hard, with some help from AMD and their "performance marking" or what they call it. I agree though, more efficient code and cooler less power consuming CPUs is (and G/VPUs for that matter) what we need right now IMO.

EDIT: That FAQ should be renamed to "Add Confusion Guide"...

 

[Lezboy]

Think of it this way at 64 bit they are sending 2x as much information per clock. Kinda like ddr for the cpu. So at 1ghz its more like a 2ghz processor when you are doing something that can take advantage of the 64bits. Very simplistic explanation but I hope it helps.

HA HA HA! That's the most ignorant made up crap I've ever heard. It's already been linked but I'll link it again because some people prefer to simply make things up then actually learn. learn something

 

[Lezboy]

Another one here It's a bit dated but still contains some good info.

 

[jema]

And why dont you prove that you know more than linking?

 

[yodayoda]

Originally posted by: jema
Works for me, thanx.

Tech docs wouldnt do me much good, Ive sneaked peaks at some of them in the past and I get FA.

The G4s are 32bit right? Apple pushing that "MHz isnt everything" pretty hard, with some help from AMD and their "performance marking" or what they call it. I agree though, more efficient code and cooler less power consuming CPUs is (and G/VPUs for that matter) what we need right now IMO.

EDIT: That FAQ should be renamed to "Add Confusion Guide"...

ok, it has been a while since i took an EE class, but here is what i remember:

the big difference between the G4s and PC is the type of instruction set. they are RISC (reduced instruction set code) and as a result the G4s have a very short pipeline (4 stage i believe). AMDs and Intels use the x86-32 instruction set which is CISC (complex instruction set code) but slightly different implementations: athlon has a 10-stage and P4 has a 20-stage pipeline. more stages in your pipeline are bad--they can decrease your IPC (intructions per clock) because they have a very big branching penalty. so while Apple chips are only at 1 GHz, they do more work per clock than AMD or Intel CPU. and likewise, why a higher clocked P4 doesn't necessarily outperform a lower clocked Athlon.

 

[pm]

This is a pretty interesting question.

The best answer that I can think of is power. If you look back over the stats of the current CPU's on the market most (with the exception of Sun) are pushing the power envelope.

Intel's Itanium 2 (McKinley) is ~130W@1GHz on a 0.18um process
Sun's Ultrasparc III is ~75W@1.05GHz on a 0.18um process
Compaq's Alpha EV7 is ~125W@1.1GHz (estimate) on a process that I can't recall
IBM's Power4 is ~125W@1.3GHz (2 cores/1 die) on a 0.13um SOI process
HP's PA-RISC is ~60-70W as I recall, but they haven't been publishing power numbers lately. Besides, they are on their third turn of the same core (or is 4th?).

As multiple papers at various conferences can attest, much of this power is in the clock tree. In the Alpha 21264 it's ~32% of the total power (Joel Emer, Compaq, HPCA00). At the ISSCC conference last year during the question and answer section, the presenter from IBM said that approximately 65% of the total power on the Power 4 is from the clock distribution network. Most other estimates that I have heard are over 1/2 of the chip power going to the clock alone.

These CPU's pack a large amount of transistors (the Itanium 2 has over 200 million transistors vs. a mere 42 million on the Pentium 4) and dissipate large amounts of power. High power dissipation results in a lot of heat that needs to be removed from the CPU, the computer, and the building, but high power also means high currents which require precision power delivery systems and packaging. These CPU's simply don't have more margin to increase the clock frequency because beyond a certain point it becomes very hard to deliver power to the CPU. As I have heard, with current technology, the limit is about 130W. Beyond that you can't effectively cool it in a multi-way rack-mount system and you can't provide power to it cost-effectively.

Question #2:
I personally think that there little point in 64-bit computing for the home user currently. Looking ahead, I suppose it's inevitable, but for now and for the near future, I can't see a strong reason for it. I can't think of any common apps offhand that would require 64-bit integers (besides which, SSE2 has support for 64-bit integer operations) and I can't see very many home users requiring more than 4GB. And even then, you can use 36-bit addressing (ESM) to address up to 64GB.


Patrick Mahoney
Microprocessor Design Engineer
(formerly on the McKinley project)
Intel Corp.
Fort Collins, CO

 

[BuddyAtBzboyz]

Think of it this way at 64 bit they are sending 2x as much information per clock. Kinda like ddr for the cpu. So at 1ghz its more like a 2ghz processor when you are doing something that can take advantage of the 64bits. Very simplistic explanation but I hope it helps.

\

Y'all are right whom linked to those stories. I hate when I stick my foot in my mouth I was in essense trying to speak about the implementation in the hammer that is supposed to do 2x 32 per clock vector computing if I read that faq correctly. I should have said something that can take advantage of the vector computing correctly instead of take advantage of the 64 bits. I guess a little knowlege and a lack of sleep is a dangerous thing Yes and I know vector computing doesn't yeild a 2x increase even when implemented properly. Sorry if I led anyone astray.

 

[jema]

Thank you pm and yodayoda, things are staring to clear up.

New Q, why does the P4 have a long pipeline if it makes it slower?

Im going to keep ytou here forever you do know that dont you?

 

[AndyHui]

A "workunit" as defined in each stage of a processor's pipeline takes a certain amount of time to do (obviously relating to the amount of hardware required to do that workunit).

Clearly, a relatively large task will take a lot of time, so for example (and a very slow example), in a single stage, single pipeline processor running at 1MHz, that workunit needs to be completed in 1 millionth of a second.

How can we speed things up? Break that large task into smaller chunks, and then line up each stage one after another. If you were to take that single task above and break it into 2 sections, then you could increase the speed to 2MHz.

With the very simplified explanation above, adding stages to the pipeline allows you to increase the clockspeed. Otherwise you end up with architectural ceilings like what happened with the Pentium 3 and what is happening now with the current Athlon design.

A long pipeline doesn't make things slower. The problem with a long pipeline is that you need to flush the entire pipeline if you have a branch mis-prediction. This means that you have wasted the instruction that is part of the way through the pipeline, and you will need to wait for the next instruction to go all the way through the pipeline, which can be very costly in terms of clock cycles.

 

[jema]

Oki, so cant you make a CPU run more that one instruction at once? So that should it fail you just cleat that one out and take on the next one. Maybe that doesnt work if the second is dependand on the first.

So this means that when CPUs either genrate to much heat or have so long pipelines that that branch prediction thingy isnt effective anymore they wont get any faster?

 

[imgod2u]

Yes you can make a CPU run more than 1 instruction at once. Through both pipelining and putting separate processes in parallel (superscalar design). You're still limited, in the x86 world, of a 3 instruction decode per clock, but from there on you can pretty much put as many pipelines in parallel as you want. How many is needed and how many would just take up space is a different story...

 

[Lezboy]

I was in essense trying to speak about the implementation in the hammer that is supposed to do 2x 32 per clock vector computing if I read that faq correctly. I should have said something that can take advantage of the vector computing correctly instead of take advantage of the 64 bits.

Well, you're in the same boat as before. Misinformation. The hammer has nothing to do with this. SSE2 allows 2x64 or 4x32 just like the velocity engine in the G4. Moving to a 64-bit CPU will have nothing to do with this. It's already here and it's the 128bit SSE2.

As for the flop that's been going around about the G4's ficticous 4 stage pipeline and its RISC nature, you're completely wrong and just guessing. The 7800 G4s and below had a 4 stage pipeline but that only took it to 400mhz. It's now much longer. I suggest that you read this You will find that the front end RISC and CISC mean absolutely nothing now and that the K7 is a RISC processor internally. Happy reading.

And why dont you prove that you know more than linking?

Well, I believe that someday people will learn to read and learn rather then just making things up. Eventually, they will learn how to look things up for themselves. Would you really rather that I just say what's in the article rather then you read it? Would you like me to chew your food for you too?

 

[Duvie]

HA HA HA! That's the most ignorant made up crap I've ever heard. It's already been linked but I'll link it again because some people prefer to simply make things up then actually learn. learn something

Lose the attitude!!! Andy handled it with a bit more tact!!! It was wrong and you correct him...PLAIN AND SIMPLE....

I see as a newer member you already are defining yourself as an arse!!!


I think his answered was too somplified and thus should have been a clue it wasn't correct...HOwever I have seen ppl around here state that a couple of times...Remember the internet and this forum is full of misinformation. So don't jump on somebody for maybe reading that information and believing it was true.

By the way your username is border line offensive!!!

 

[Lezboy]

By the way your username is border line offensive!!!

You find lesbians offensive? You're a strange little nerd.

 

[Duvie]

You find lesbians offensive? You're a strange little nerd.

NO jackoff!!! NO place in an hardware information forum for stuff like that, period....

 

[Lezboy]

Yeah I guess that lesbians shouldn't be allowed in hardware forums. God forbid that a tomboy lesbian should identify themselves in these forums!!!! That would just offend to many NAZIS! While we're at it, let's strike out in a xenophobic fashion at "MuslimJoe."

 

[Lezboy]

Follow-up Q Nr2: Is there any point in running 64bits for home/office use? What I've been told is that we're not really using the 32bits we got to the max.

That's a difficult question. Right now I'd say no. BUT I would also look at history. When windows 3.1 and 16bit was where it was at and such amazing games as X-Wing were the top of the top the media was poo pooing 32bit to an extent saying that it simply wasn't necessary for word processing and would likely only be stuck in high end workstations. Of course, they were wrong. There are some types of applications where 64 bit processing provides great benefits which might someday make it to the average person's desktop.

 

[jema]

Excuse me but what the &%&% are you trying to do with this topic?

And to answer your question, no I dont want information just relayed I want it explained to me. Why else do you think I ask? Seems pretty dumb to assume that just because someone can read they will understand everything they read, a point I belive you have proved beyond any doubt.

 

[Lezboy]

You're an ungrateful little prick. You ask for info on 64 bit processing. I provide THREE links and write you two paragraphs and this is what I get? I'll make sure to ignore any threads you post in the future.

And why dont you prove that you know more than linking?

Sorry, I didn't think that providing articles for you to read wasn't a valid answer. I'll try to conform to your rigid yet unexplained answer format.

---

And you are a rude, hostile noob who has no clue how to make friends.

Good bye,

AnandTech Moderator

 

[Lezboy]

Follow-up Q Nr1: Where will the Opteron end up in all this? If it is some sort of technical speed limit will it then run the core at different speeds or is it one speed and some sort of code conversation for 32bit?

I would suggest that you read some articles on the hammer core. The hammer core will run at one speed across the die. What they've basically done is extend the existing 8 registers from 32 to 64 bit and add another 8 64 bit registers. It has 64 memory addressing and instruction pointer. When 32 bit apps are run they will only use the "old" 8 32 bit registers and when 64 bit apps are used (under a 64 bit OS) they will take advantage of 16 64bit registers. There will be no change in clock speed from 32bit to 64 bit.

 

[Lezboy]

To answer the original question, I don't think that 64 bit processors are so limited in clock speed because of manufacturing limitations. Taking into consideration what 64 bit processors are used for, raw mhz are not as important as more registers and cache. Id you're concerned about the hammer, the x86-64 extension to the athlon core (which is what the hammer is overly simplified) takes up a tiny percentage of the core space and will not contribute excessivly to heat or power requirements. The hammer should be able to scale slightly faster (it's pipeline was extended by 2 stages) then the Athlon using a newer manufacturing process (SOI.) AMD claims that the hammer core will be 20-30% more efficent then the K7 archtiecture. Who knows how true this is and what kind of hammer they're talking about but AMD is definitely going the IPC road. Don't worry about AMD not being able to scale just because the processor is 64 bit. It will be able to scale as well or better then the K7 core.