6 Phenom II cores for the price of 4

[james 1]

http://www.hexus.net/content/item.php?item=24259

if the Phenom II X4 960 does cost £120 it will be very tempting, but I have a Phenom II X3 720 and that did not unlock

 

[aigomorla]

can u unlock them tho?

B4 u go off and buy one.. i would wait to see how the core scales in relations to the PH2.

If u have a clock per clock advantage, then i would be a very tasty upgrade.

 

[heyheybooboo]

It will be interesting to see how Zosma compares to something like the 945 Deneb because of the new gates, turbocore, etc. I imagine it might clock a bit higher on lower voltage and look 'good' on more single-threaded benchies.

I imagine AMD will continue to move away from the core-unlocking chip lottery but a small part of them recognize the marketable aspect of it (even though they 'pretend' to downplay it).

Everybody loves something for free -- LOL




--

 

[richierich1212]

Well initially some 890 boards didn't have the unlocking feature, but now some manufacturers are adding it back in via BIOS updates. lol.

 

[soccerballtux]

can u unlock them tho?

B4 u go off and buy one.. i would wait to see how the core scales in relations to the PH2.

If u have a clock per clock advantage, then i would be a very tasty upgrade.

It'll probably scale 50% at the same clock rate. They'll be sharing the L3 cache, but this time it's clocked at 2.4ghz not 2.0ghz.

 

[aigomorla]

It'll probably scale 50% at the same clock rate. They'll be sharing the L3 cache, but this time it's clocked at 2.4ghz not 2.0ghz.

this is the million dollar question for me... and yet not 1 person can point me to accurate numbers..

 

[Martimus]

It'll probably scale 50% at the same clock rate. They'll be sharing the L3 cache, but this time it's clocked at 2.4ghz not 2.0ghz.

The few screen shots I have seen have the stock L3 at 2.0GHz still on the X6.

Also, cores do not scale linearly, so getting scaling data from the x6 and comparing it to an x4 isn't exactly going to give you much. You could calculate what it should be using that equation IDC posted a while back, and that will give you a ball park figure of what the Thuban version of the X4 would do.

 

[soccerballtux]

The few screen shots I have seen have the stock L3 at 2.0GHz still on the X6.

Also, cores do not scale linearly, so getting scaling data from the x6 and comparing it to an x4 isn't exactly going to give you much. You could calculate what it should be using that equation IDC posted a while back, and that will give you a ball park figure of what the Thuban version of the X4 would do.

I'm assuming perfectly multi-threaded code, because otherwise and we're discussing software capabilities not hardware.

There are no hard numbers but if the L3 is 2.4Ghz (which I heard but if it's 2Ghz then that is disappoint), then in total these 6 cores will probably perform 50% or better than X4 Ph2 cores with a 2Ghz L3 cache. You can trust me on that, I'm not a fanboy I just call it like I see it. If the L3 is still at 2Ghz then no, these aren't going to scale linearly (ie 1.5 * Ph2 X4 @ 3Ghz), because we'll see what we saw with the X3 vs X4's...cache was divided among more cores and so performance suffered (not a lot, but still suffered).

I'm probably going to hold onto my X3->X4 chip until Bulldozer (or longer), or move to a 6-core when Bulldozer comes out.

 

[DrMrLordX]

I'm assuming perfectly multi-threaded code, because otherwise and we're discussing software capabilities not hardware.

That's not entirely true.

Thuban has the same amount of L3 as Deneb, so we're talking 1MB L3 per core on Thuban vs 1.5MB L3 per core on Deneb. Scaling won't be perfect.

Furthermore, while we are talking about a 1P desktop chip here rather than a 2-8p server chip, I remember reading that Istanbul (and Magny Cours) rely on L3 to maintain cache coherency and/or reduce inter-core/inter-socket traffic. On some of the beefier Opteron rigs, you can commit a certain amount of L3 per socket to facilitate this process . . . or something along those lines.

I doubt that we're going to see features like that popping up in BIOSes supporting Thuban, but with 50% more cores all churning away in what will hopefully be some sort of harmony, it is safe to assume that an even larger amount of the chip's L3 will be committed to cache coherency when all six cores are pegged (vs. Deneb anyway). So . . . scaling won't be perfect.

It will not be slower by any means, especially thanks to turbo and possibly other enhancements, but don't expect perfect scaling from 4->6 cores in heavily-threaded apps. It needs more L3 for that to happen.

 

[soccerballtux]

That's not entirely true.

Thuban has the same amount of L3 as Deneb, so we're talking 1MB L3 per core on Thuban vs 1.5MB L3 per core on Deneb. Scaling won't be perfect.

Furthermore, while we are talking about a 1P desktop chip here rather than a 2-8p server chip, I remember reading that Istanbul (and Magny Cours) rely on L3 to maintain cache coherency and/or reduce inter-core/inter-socket traffic. On some of the beefier Opteron rigs, you can commit a certain amount of L3 per socket to facilitate this process . . . or something along those lines.

I doubt that we're going to see features like that popping up in BIOSes supporting Thuban, but with 50% more cores all churning away in what will hopefully be some sort of harmony, it is safe to assume that an even larger amount of the chip's L3 will be committed to cache coherency when all six cores are pegged (vs. Deneb anyway). So . . . scaling won't be perfect.

It will not be slower by any means, especially thanks to turbo and possibly other enhancements, but don't expect perfect scaling from 4->6 cores in heavily-threaded apps. It needs more L3 for that to happen.

the cache is 20% faster