533MHz FSB versus 1066MHz Memory Bus

[LowLight76]

I have an Asus P4T533 mobo. The FSB speed is 133MHz quad-pumped, which comes to 533MHz, and is 64-bits wide; thus giving me a maximum bandwidth of 4.2GB/sec between the CPU and the MCH. Ok, having said that...the bus speed between the two 232-pin RIMM sockets and the MCH is 1066MHz (which I assume is 8x133MHz), and is 32-bits wide; again giving me 4.2GB/sec bandwidth between the memory and the MCH. My questions is this: Why not make the bus between the two 232-pin RIMM sockets and the MCH identical to the bus between the MCH and CPU? If the memory bus were 64-bits wide then the memory clock speed could be lowered to only 533MHz. Obviously there's a reason for this not being done. Someone please point it out to me. Thanks.

 

[Athlon4all]

First off, the 32-bit RIMM's run at 533x2 (533MHz DDR) and is what you're asking why have a 133x4x64-bit's front side bus and a 533x2x32-bit Memory bus? Well different technologies. RDRAM was built to in part have significantly lower pincount than DDR/SDRAM, and having only 32-bit bus width makes the pin count lower (and in actuality, the 850e's MCH is really dual channel 16-bit (ie there are 2 16-biut channels going to the RIMM slots, but thats something else that I will gladly explain if you would like me to). And RDRAM because it is a serial architechure and can attain 533MHz DDR speeds, it can afford to be on only a 32-bit bus and still get high enough bandwidth. In the case of DDR SDRAM, it is maxing out at only 166MHz DDR on a 64-bit bus and the only way DDR can match RIMM4200/Dual Channel PC1066 bandwidth numbers is by going to a Dual Channel Configuration (essentially, a 128-bit bus). In a Dual Channel Configuration (Which is what upcoming VIA P4X600, SiS 655, and Intel Granite Bay and Springdale all use), DDR266 (133x2) can reach the same bandwidth numbers as RIMM4200/Dual Channel PC1066. I pray you understand now. I am gonna gom into dual channels for a second.

Dual Channel's can be impleemeneted with both RDRAM and DDR. Simply put, it runs 2 paths of equal bus width (in the case of DDR 2 64-bit paths, for RDRAM 2 16-bit paths) and they both go to different DIMM/RIMM's. The end result is that these 2 paths effectively double the theoretical maximum of bandwidth of the bus (ie current DDR266 on i845e gets 2.1GB/s of memory bandwidth, DDR266 on Dual Channel Granite Bay will get 4.2GB/s). Thats essentially how Dual Channels work. Now, Dual Channel memory controllers do have disadvantages. First, you must install DIMM/RIMM's in pairs of equal quantity. Users don't like this, but it is somewhat made up for in that most dual channel boards have 4 Memory slots. Secondly, it costs more. It is right now the only way that Intel and co can produce memory solutions that can feed enough memory bandwidth to the P4's front side bus.

Now, to add to the confusion further, your system (which uses 32-bit RIMM's (aka RIMM4200)) is a bit different than most dial channel configurations. It still is dual channels. What the 32-bit RIMM does is instead of running the 2 16-bit paths to 1 RIMM each, with 32-bit RIMM's, they put from what I understand 2 RIMM's on one RIMM stick, and then these 2 16-bit paths run both to a single RIMM. What this translates to is the removal of the need to install RIMM's in pairs (it also cuts the RIMM slots to 4 typically). Beyond that, there really is no difference in terms of bandwidth.

I pray this has helped you understand more about all this. Please feel free to PM/email/IM me if you would like me to explain it again so you can understand it God Bless

 

[LowLight76]

I didn't realize that my RIMM4200 memory transferred data on the rise and fall of the clock signal. I thought only DDR SDRAM did that. Knowing that my memory bus actually operates at 533MHz, and that data is moved on the rise and fall of the clock signal makes much more sense to me than thinking the bus literally operated at 1066MHz. I guess I'm just surprised to learn that RDRAM operates somewhat similar to DDR SDRAM, in that it transfers data on the rise and fall of the clock signal.

One more question: You mentioned that RDRAM uses a serial architecture. What does DDR SDRAM use?

 

[Athlon4all]

You mentioned that RDRAM uses a serial architecture. What does DDR SDRAM use?

To answer that, I think Im going to point you to an excellent artcile done by Ace's Hardware, titled Ace's Guide to Memory Technology: Part 3. Essentially, the compare and contract RDRAM and DDR. Great article, a tad technical, but it should through God help explain this to you. I will be glad to answer any additional questions