Question 5 Nodes in 4 years discussion

[Markfw]

I agree. Intel can talk all they want about how good nodes are in the lab, but they did that with 10nm so we know the game. Until mass quantities of chips are delivered in products you can't claim a node has been "delivered".

I totally agree. Its like an ES chip does not mean a product is ready or can be sold. The first AMD 7551 ES chip I bought had to work on one motherboard only, and with one specific BIOS and it was a PIG.

 

[H433x0n]

FWIW, Intel's "5 nodes in 4 years" just means they need to hit the "manufacturing ready" milestone, which may be MONTHS ahead of the first product on the shelves. I'm not sure if "manufacturing ready" means ready for high volume manufacturing or if it just means an earlier milestone but the differentiation is important. I suspect that even if Intel 18A achieves decent yields by H2 2024, the first products won't be on shelves until late H1 2025.

View attachment 86322

eh, they only just crossed off Intel 4 at the Innovation presentation. This is despite them saying it was manufacturing ready 6+ months ago. It sounds like they'll only consider the nodes done once it's in high volume manufacturing.

 

[H433x0n]

I would add that TSMC's N3 problems could make it more likely that Intel has similar issues. That is, if it turns out TSMC's problems were more due to limitations of EUV technology itself rather than screwups on the part of their engineers.

That’s not how it works. They all pull different levers to reach their desired scaling. There’s different chemistry involved too.

They don’t even always use the same EUV machine. For all we know Intel is using exclusively NXE:3800E for 18A, that makes their job easier than it was for TSMC using NXE:3600D for N3B. It’s inherently more difficult to reach the scaling TSMC was going for with Finfet and traditional power delivery compared to GAAfet and BPD.

 

[igor_kavinski]

View attachment 86322

When was this slide made public? The time period elapsed since to December 2023 should be how long it will take Panther Lake to be available for sale after H2 2024, if Intel stays consistent.

 

[Mopetar]

If you only care about how it performs why read/post in tech forums? I'm being serious.

Because once companies head down this path there's nothing to stop them from having "new" nodes every month. Made a few minor adjustments to your EUV machine? Call it a whole new node!

I've become a lot less interested in following process tech as companies have gone down this route and are using it to generate publicity or worse yet play games like this.

Intel gets some guff for having 14nm+, 14nm++, etc. but it was considerably more honest than what they and TSMC are doing now.

They aren't really getting 5 nodes in 4 years. Historically a new node was as the very least a half-shrink (half-node) and normally implied achieving the doubling in density proscribed by Moore's law. If Intel could get a 16x (five doublings) in 4 years that would be one of the most amazing feats of engineering in the history of semiconductors. That isn't what's happening though.

 

[Saylick]

When was this slide made public? The time period elapsed since to December 2023 should be how long it will take Panther Lake to be available for sale after H2 2024, if Intel stays consistent.

I think it was late 2022 when that slide was made public. Don't quote me on that, though.

 

[Geddagod]

Per TSMC, N3E (the version most people will be using) has 3-8% more performance than N3B. There’s almost no scaling difference between N4P and N3E sans DTCO

This is the bar that Intel 18A has to clear. If 18A manages to get >10% better performance than N4P they’ll have process leadership next year.

Don't think that graphs hold up, aren't the architectures different? I wouldn't be so quick to blame TSMC.
Also a more direct comparison between PPA of Intel and TSMC would be seen with ARL. Just need to wait a year.

AFAIK Intel 3 is meant only for Sapphire and Granite Rapids. Do you have any thoughts as to why they are seemingly skipping that node for client?

Why use Intel 3 when you could use Intel 20A (for ARL)?

I'm assuming that is still cancelled and all you will see is Arrow Lake at TSMC

Rumor still is that ARL-U is MTL refreshed, though idk if it will be Intel 4 or Intel 3. Don't think it's cancelled

The thing is, TSMC Finflex seems a much more affordable and higher-yielding solution.

Based on what? It's lauded for allowing greater flexibility (so better optimization for perf/watt) not for it's ability for greatly increasing yields

So is it still 18A, or more of a 20A+? Since Intel is seemingly pulling 18A in because high-NA isn't ready do we credit them for being on time, or do we blame Intel by saying 18A isn't what was originally promised?

Intel mentioned that Intel 18A never required high NA to work. It was completely optional. Pretty sure it's just used to improve yield/reduce complexity of the fabbing process, not actually changing any specs.

5 nodes in 4 years is marketing speak. In reality it’s 2 nodes in 4 years with Intel 4/3 and Intel 20A/18A being the 2 separate nodes.

Intel 20A/Intel 18A is not really a separate node from Intel 4/Intel 3. Same thing with TSMC 2nm vs TSMC 3nm. Though I'll eat my words if that level of density shrinks start becoming the norm.

Does Samsung not have a chance of gaining the process leadership?

Funnily enough Samsung also has been claiming that they will gain leadership in 2025 IIRC, just like Intel

Also for some reason I have an uneasy feeling that something could be up with Meteor Lake.

You sure it's not some uneasy hope that something could be up with MTL? lol

It's kind of strange that Intel provided so much data but absolutely no performance data.

Perf gains are like nonexistent for MTL to be fair.

Seems like they are still trying to get performance to where it needs to be

Really? What about all the GB6 leaks of MTL online? These can be found publicly I'm pretty sure. MTL is hitting 5GHz already in ST, and it's max frequency is rumored to only be a 100-200MHz higher.

but if they are releasing in December then wouldn't parts already have been getting binned for quite some time now?

Not if they don't have volume. Didn't they announce they are a bit behind in converting one of their fabs to Intel 4? IIRC they only have one site where they are in HVM with Intel 4.

TSMC supposedly had N3B in "production" this entire year but with the only known product on that node shipping last week it is hard to claim anything else other than N3B was delivered in Sept 2023.

What's the problem with TSMC saying that? I don't see anything wrong about it. You do know stuff takes a while to ramp, right? I mean it's valid to say a node isn't complete until the product is launched, sure, but that doesn't mean companies have to be lying when they say there are in "HVM". Those things aren't mutually exclusive.

Given that Meteor Lake is hardly a big architectural change any issues that restrict performance or have delayed its launch pretty much have to do with the process not the chip design.

Glances at MTL "C0" steppings
Sure... there are no problems with the chip design... sureeeee

TSMC's issues with N3 have a lot of Intel boosters excited that Intel will retake the lead, as if Pat Gelsinger can wave a magic wand and erase all the issues that caused Intel's fabs past difficulties.

It did set back the "working" N3 node by a year, so yes, it really did help Intel's chances. Maybe not directly, but to pretend that TSMC falling behind isn't indirectly helping Intel is dumb.

TSMC had years of successful problem-free experience with EUV until they ran into significant issues with N3.

Intel had years of success problem-free experience with DUV too...

I would add that TSMC's N3 problems could make it more likely that Intel has similar issues. That is, if it turns out TSMC's problems were more due to limitations of EUV technology itself rather than screwups on the part of their engineers.

Looks like N3B is bad because they tried using too much EUV. Pretty sure Intel 4 is rumored to use drastically less EUV layers than N3B.

 

[Doug S]

Glances at MTL "C0" steppings
Sure... there are no problems with the chip design... sureeeee

You're making the assumption that process problems at Intel can only be fixed by changing the process, rather than by revving the design to rework the places where problems occur. Intel has traditionally had far more integration between their process side and chip design side that allow that sort of back and forth than is possible in a foundry. They aren't a foundry with Intel 4 so they can cross those lines if they think it gets them to a solution more quickly.

Heck I wouldn't be shocked if Apple was forced to make revisions to A17 to work around some of the issues observed with N3B. Just look at that Asianometry video regarding the stochastic print errors. That's something that could quite conceivably be addressed by changing your masks - perhaps the circuit level design doesn't change but some changes are made to the computational lithography software to tweak the masks being produced to mitigate those print errors.

 

[Geddagod]

You're making the assumption that process problems at Intel can only be fixed by changing the process, rather than by revving the design to rework the places where problems occur.

That's exactly what Intel 10nm did lol (changing process).
But ye, it's definitely weird Intel 4 is their highest yield during launch quarter as well for such a problematic node... and benches that show MTL hitting 5GHz too... Oh, and one could press that Intel was only able to make that yield claim because they are launching Q4 rather than Q3, but the difference in yields in comparison to other ticks appear to be substantial.
But ye, it's not like Intel has any history of design delays due to issues not related to foundry, right? (sapphire rapids crying in the corner)
Your claim that Intel 4 facing issues is the most likely reason for MTL being delayed is, IMO, wrong. Even your original claim that since the architecture didn't change, MTL should be easier on the design side vs the fab side, that's also wrong. Foveros? Tile disaggregation? VPU? Massive changes. Adding architecture changes on top of that would frankly have been too much. Biting off too much one can chew is prob one of the biggest reasons SPR got delayed so hard as well.
For bad nodes, we usually get rumors from the rumor mill abt the node being bad. Most recently for N3B, for example, there were rumors months before that N3B was not yielding very well. And while there was a lot of talk about MTL being delayed, there wasn't really ever much talk about Intel 4 being the problem.
In conclusion, while it's fine to cast suspicion on Intel 4 due to MTL's late launch, saying that it's the most likely reason is, again, IMO, wrong. Just doesn't make much sense.

 

[H433x0n]

Don't think that graphs hold up, aren't the architectures different? I wouldn't be so quick to blame TSMC.
Also a more direct comparison between PPA of Intel and TSMC would be seen with ARL.

The architectures are ~80% the same. It’s basically the same CPU with a meager 3.5% IPC boost. I’m assuming at iso frequency the new core is slightly more power hungry and the initial yields are bad and that’s why I attributed a 10% improvement over N4P which I think is slightly optimistic since on paper the A17 chip shows perf/watt breaking even.

Put it this way, there was a tangible perf/watt improvement going from A15 (N5P) -> A16 (N4P) that’s larger than what’s shown with the A17 (N3B) chip.

 

[Doug S]

The architectures are ~80% the same. It’s basically the same CPU with a meager 3.5% IPC boost. I’m assuming at iso frequency the new core is slightly more power hungry and the initial yields are bad and that’s why I attributed a 10% improvement over N4P which I think is slightly optimistic since on paper the A17 chip shows perf/watt breaking even.

Put it this way, there was a tangible perf/watt improvement going from A15 (N5P) -> A16 (N4P) that’s larger than what’s shown with the A17 (N3B) chip.

I still think node variation is the real culprit for the A17's power draw - that's why there is a difference of opinion about whether their iPhone 15 Pro overheats. Many are saying theirs can get hot, but some are saying theirs barely gets warm. If the "known good dies" TSMC is supplying have a wider than desirable range of voltages required to operate (but mostly on the higher side) at the target frequency that's exactly what you'd see. I don't know enough about the physics of semiconductors to guess whether stochastic print errors could cause that sort of variation.

Of course something completely different could be to blame for the observed behavior - maybe there's a bug in iOS 17 that can cause a background kernel thread runaway in some cases or something, but if that's the case it'd be addressed no later than 17.1 so we'd know before long.

 

[H433x0n]

I still think node variation is the real culprit for the A17's power draw - that's why there is a difference of opinion about whether their iPhone 15 Pro overheats. Many are saying theirs can get hot, but some are saying theirs barely gets warm. If the "known good dies" TSMC is supplying have a wider than desirable range of voltages required to operate (but mostly on the higher side) at the target frequency that's exactly what you'd see. I don't know enough about the physics of semiconductors to guess whether stochastic print errors could cause that sort of variation.

It was rumored to have had poor yields so Apple had to accept a lot of chips they wouldn’t have otherwise to get adequate supply. I’m sure a lot of these chips are suboptimal and running higher than ideal voltage.

No doubt yield will get better with N3E and the wide spread use of NXE:3800E.

 

[coercitiv]

Poor parametric yields would also explain why Apple still pushed the chips at launch, they did not clock the chips lower because they expect quality to improve. If it does not, they can always push an update and shave clocks a bit.

That being said, it kind of alienates their best paying customers: early adopters, premium device buyers. I guess it does not matter much if it happens on rare occasions.

 

[Hulk]

With Intel cancelling 20A I thought it might be interesting to rekindle this thread.
Maybe 4 nodes in 4 years?

 

[DavidC1]

With Intel cancelling 20A I thought it might be interesting to rekindle this thread.
Maybe 4 nodes in 4 years?

18A with 15% perf over 3 and 30% density is a big disappointment. 18A was supposed to be 10% over 20A, not 15% over 3.

Intel 3 is ok but the density gain is merely 10% because of having the so-called HD library. Intel claimed that Intel 3 was supposed to have density gains on the high end.

2 nodes in 4 years, with plusses in between. And imagining betting the farm on that.

 

[Joe NYC]

With Intel cancelling 20A I thought it might be interesting to rekindle this thread.
Maybe 4 nodes in 4 years?

The first node, "Intel 7" was never really one of the achievements of 5 nodes in 4 years, it was the starting point, and Intel counted it as 1.

 

[DavidC1]

The first node, "Intel 7" was never really one of the achievements of 5 nodes in 4 years, it was the starting point, and Intel counted it as 1.

It's Intel 4, then 4+, then 20A, and then 20A+. Two plusses and two nodes.

 

[Hans Gruber]

Intel was poised to take the lead and just fell on their face and out of the race. It appears Asia is #1 in semiconductors. I suspect 20A fell behind whatever TSMC process they were benchmarking against in lab comparison tests. My guess is N4P. I am more confused than ever with the CPU race. In no way am I knocking TSMC. I just thought Intel was going to make good on their node process with 20A. 18A is only 10% better than 20A was supposed to be. That does not bode well for 18A unless they were having serious yield issues. 20A was always supposed to be a short lived process. 18A is going to be around for 3 or 4 years. Let's hope they figure out their mess.

 

[DavidC1]

Intel was poised to take the lead and just fell on their face and out of the race. It appears Asia is #1 in semiconductors. I suspect 20A fell behind whatever TSMC process they were benchmarking against in lab comparison tests. My guess is N4P. I am more confused than ever with the CPU race. In no way am I knocking TSMC. I just thought Intel was going to make good on their node process with 20A.

You missed this:

Speculation but it seems good as any.

Whether due to execution sucking or finances not allowing it, they couldn't get extra 10% for 18A over 20A, nevermind extra density.

Therefore, in the spirit of trying to reduce costs, they took 20A, added extra libraries, and renamed it 18A. Hence 18A is only 15% over Intel 3, same as the original claims for 20A. What do you do with the 20A naming? Cancel it!

When morality of a nation falls, the fall of a country is not too far behind.

 

[FlameTail]

Therefore, in the spirit of trying to reduce costs, they took 20A, added extra libraries, and renamed it 18A. Hence 18A is only 15% over Intel 3, same as the original claims for 20A. What do you do with the 20A naming? Cancel it!

Well, this is bad.

Can Intel Foundry take the process node leadership from TSMC then?

 

[Hans Gruber]

You missed this:

Speculation but it seems good as any.

Whether due to execution sucking or finances not allowing it, they couldn't get extra 10% for 18A over 20A, nevermind extra density.

Therefore, in the spirit of trying to reduce costs, they took 20A, added extra libraries, and renamed it 18A. Hence 18A is only 15% over Intel 3, same as the original claims for 20A. What do you do with the 20A naming? Cancel it!

When morality of a nation falls, the fall of a country is not too far behind.

I hear you. 18A brings the backside power delivery. 20A was supposed to be proof of concept type silicon. Remember the days when Intel would never consider outsourcing their processors to fabs from outside companies. In my mind, Intel has already lost this round for outsourcing their silicon to TSMC. We already know TSMC makes real good silicon. Intel is acknowledging this by using TSMC.

I am seriously disappointed.

 

[dttprofessor]

Well, this is bad.

Can Intel Foundry take the process node leadership from TSMC then?

It depends on 18a&14a,not 20a.

 

[DavidC1]

I think they said 18A-P is 10% perf, so the variants are basically the original 18A.

 

[desrever]

The 5 nodes in 4 years is just

10nm SF+ (Intel 7) - shouldn't even count since the products we basically already launched when they announced 5N4Y
broken 7nm (Intel 4) - late and terrible
7nm+ (Intel 3) - late
broken 5nm (20A) - cancelled
5nm+ (18A) - late and reduced performance

5N4Y was announced in July 2021, if Intel doesn't deliver 18A on time (before July 2025), which may or may not happen, we have basically have 1 real node, Intel 7nm, delivered in the 4 years window.

At this point, 18A probably can't even properly compete with N3 class nodes. Probably will comparable to N5 class nodes. Can't wait to see products on it regress in performance/watt from Intel moving from N3 to 18A.

 

[DavidC1]

At this point, 18A probably can't even properly compete with N3 class nodes. Probably will comparable to N5 class nodes. Can't wait to see products on it regress in performance/watt from Intel moving from N3 to 18A.

I think that's an exaggeration, but likely with the reduced figures that they'll do N3 but a year later.

Intel nodes are optimized for high power/high frequency so for Lunarlake like products they'll lose perf/w.

But the real loss is not process, but accountants/finance or whatever dumbo that decided Lunarlake level battery life is not worth more than one generation. Pantherlake is just repeating what they have done since 2013, nothing new.