4Ghz on .832 volts?

[deputc26]

http://techreport.com/discussions.x/17258
I believe Intel has stated a 20% power reduction in the move to 32nm from 45nm. I believe D0 i7s usually need at least 1.25v to reach 4.0ghz. Given that power required is proportional to the square of voltage (1.25/.832)^2 =2.25 or a 125% reduction in power required at 4.0 ghz.

This is clearly not possible.

Regardless, the google translation of the oriental link was hilarious:laugh: and Intel's 32nm process is looking very good.

 

[soccerballtux]

I think you might have the math a little wrong...
P = V^2/R

If P decreases by 20%, then the term V^2 must decrease by 20%. This means voltage would be going from 1.25v to sqrt(1.25v), or 1.12v.

 

[deputc26]

Originally posted by: soccerballtux
I think you might have the math a little wrong...
P = V^2/R

If P decreases by 20%, then the term V^2 must decrease by 20%. This means voltage would be going from 1.25v to sqrt(1.25v), or 1.12v.

You are just stating it backward (relating V logarithmicly to P instead of P exponentially to V), from your equation:
P= V^2/R
I will arbitrarily assign 100w to equal P and solve for "r" with 1.25v
100w = (1.25^2)/r
100w = 1.5625/r
r = .015625

Now substituting .832v for 1.25v and using calculated value for r

P = (.832^2)/.015625
P = .692224/.015625
P = 44.3w
100w/44.3w = 2.25

Of course it's not this simple but all other things being equal, the above change in voltage would cut power consumption to less than half, which would be truly unbelievable (which is why I don't believe it). I'm secretly hoping someone will tell me it's possible

 

[ilkhan]

As I recall TDP is proportional to the square of voltage, and linear to clock speed. But thats off of my shaky memory.
4Ghz at 60% of the TDP would be far better than my quad at 2Ghz.

 

[taltamir]

i find it highly suspect that the change is exactly to the power of two... why not 2.0352342? or even f(x)^g(x)

 

[PM650]

Originally posted by: ilkhan
As I recall TDP is proportional to the square of voltage, and linear to clock speed. But thats off of my shaky memory.
4Ghz at 60% of the TDP would be far better than my quad at 2Ghz.

This is correct.

The power dissipated by a single cmos inverter is P = fCV^2, where C is the gate capacitance, f is frequency. Multiply that by some arbitrarily chosen value n of how many complimentary/cmos pairs you expect to be operating and you have the power requirement. Clearly, moving from 45nm -> 32nm reduces certain device characteristics, i.e. gate capacitance & threshold voltage.

 

[MarcVenice]

If you scroll all the way down here: http://www.techpowerup.com/998..._4_GHz_at_0.832_V.html

You will see the voltage at 1.248V. My guess is that under load it needs 1.248V. I think this is very nice, but not surprising from what Intel has been telling us about 32nm. I think 0.832V is probably when idling.

 

[dmens]

yeah that is idling voltage. it's faster than D0, just can't say how much.

 

[drizek]

So does it undervolt without underclocking at idle? Or are the numbers just a bios bug for now?

 

[soccerballtux]

Originally posted by: deputc26

Originally posted by: soccerballtux
I think you might have the math a little wrong...
P = V^2/R

If P decreases by 20%, then the term V^2 must decrease by 20%. This means voltage would be going from 1.25v to sqrt(1.25v), or 1.12v.

You are just stating it backward (relating V logarithmicly to P instead of P exponentially to V), from your equation:
P= V^2/R
I will arbitrarily assign 100w to equal P and solve for "r" with 1.25v
100w = (1.25^2)/r
100w = 1.5625/r
r = .015625

Now substituting .832v for 1.25v and using calculated value for r

P = (.832^2)/.015625
P = .692224/.015625
P = 100w/44.3w = 2.25

Of course it's not this simple but all other things being equal, the above change in voltage would cut power consumption to less than half, which would be truly unbelievable (which is why I don't believe it). I'm secretly hoping someone will tell me it's possible but

Oh so you're saying the website says 0.832v? I thought you had calculated that yourself and concluded that "a 20% reduction in power means vcore must be 0.832v".

 

[ilkhan]

no it says .832v.
We cant see a taskbar, but something could be running minimized to be using the cores.

edit: If you scroll down theres more screenshots. The .832v is indeed idle power. Load is 1.248v. Significant difference. I want to see the 5Ghz numbers.... We've seen 10s superpi results before, but thats pretty impressive regardless.

 

[deputc26]

Originally posted by: taltamir
i find it highly suspect that the change is exactly to the power of two... why not 2.0352342? or even f(x)^g(x)

I agree, I have simply never seen a more precise relationship between the two published.

Originally posted by: MarcVenice
If you scroll all the way down here: http://www.techpowerup.com/998..._4_GHz_at_0.832_V.html

You will see the voltage at 1.248V. My guess is that under load it needs 1.248V. I think this is very nice, but not surprising from what Intel has been telling us about 32nm. I think 0.832V is probably when idling.

Ahh! that sounds much better/ more realistic.

 

[aigomorla]

coolalar and Jcornel are my heros..

no joke...

compared to them i am a normal user.

 

[ArizonaSteve]

Google translate needs some work...

"Standing on the top -155 degrees was cold and lonely world"

"AMD fans who do not look at his beloved wife of the 2009 battle with the animal"

Hilarious.

 

[Idontcare]

Originally posted by: deputc26

Originally posted by: taltamir
i find it highly suspect that the change is exactly to the power of two... why not 2.0352342? or even f(x)^g(x)

I agree, I have simply never seen a more precise relationship between the two published.

Originally posted by: MarcVenice
If you scroll all the way down here: http://www.techpowerup.com/998..._4_GHz_at_0.832_V.html

You will see the voltage at 1.248V. My guess is that under load it needs 1.248V. I think this is very nice, but not surprising from what Intel has been telling us about 32nm. I think 0.832V is probably when idling.

Ahh! that sounds much better/ more realistic.

Guys take a look at this thread and the included empirical data.

(I'll quote myself here for the folks who don't want to scroll thru the linked thread)

Originally posted by: Idontcare
Here you go, Vcc versus power consumption at the wall for my system.

http://i272.photobucket.com/al...usPowerConsumption.gif

Note that the coefficients for both the squared and linear terms are practically zero (10^-9 and 10^-6). The y-intercepts represent system power consumption in the absence of the CPU (so chipset, ram, hdrives, vidcard, fans, PSU efficiency, etc) - comes in the vicinity of 105-120W which is reasonable for my components.

If I force the fit to be quadratic I get non-physical y-intercepts, 700W in one case and 14W in the other, neither of which could possibly be my system level power consumption so this counts as a second peice of evidence that quadratic power scaling for my system is not correct.

So in conclusion, for a 65nm Kentsfield quadcore chip, my results corroborate the lost circuits claims that power consumption scales as the cube of cpu voltage, not the square.

For those of you familiar with the application of Taylor series expansion, the X^2 correlation between voltage and power consumption was simply the dominate term in the expansion for the practical range of applied voltages to the CMOS devices of historic relevance.

But the third, fourth, and higher order terms were always there, albeit with near-zero coefficients out front so the contribution to the overall power consumption historically had been negligible and one was safe to ignore them (and to teach others to ignore them by way of never mentioning them in the first place).

 

[MarcVenice]

Originally posted by: Idontcare

Originally posted by: deputc26

Originally posted by: taltamir
i find it highly suspect that the change is exactly to the power of two... why not 2.0352342? or even f(x)^g(x)

I agree, I have simply never seen a more precise relationship between the two published.

Originally posted by: MarcVenice
If you scroll all the way down here: http://www.techpowerup.com/998..._4_GHz_at_0.832_V.html

You will see the voltage at 1.248V. My guess is that under load it needs 1.248V. I think this is very nice, but not surprising from what Intel has been telling us about 32nm. I think 0.832V is probably when idling.

Ahh! that sounds much better/ more realistic.

Guys take a look at this thread and the included empirical data.

(I'll quote myself here for the folks who don't want to scroll thru the linked thread)

Originally posted by: Idontcare
Here you go, Vcc versus power consumption at the wall for my system.

http://i272.photobucket.com/al...usPowerConsumption.gif

Note that the coefficients for both the squared and linear terms are practically zero (10^-9 and 10^-6). The y-intercepts represent system power consumption in the absence of the CPU (so chipset, ram, hdrives, vidcard, fans, PSU efficiency, etc) - comes in the vicinity of 105-120W which is reasonable for my components.

If I force the fit to be quadratic I get non-physical y-intercepts, 700W in one case and 14W in the other, neither of which could possibly be my system level power consumption so this counts as a second peice of evidence that quadratic power scaling for my system is not correct.

So in conclusion, for a 65nm Kentsfield quadcore chip, my results corroborate the lost circuits claims that power consumption scales as the cube of cpu voltage, not the square.

For those of you familiar with the application of Taylor series expansion, the X^2 correlation between voltage and power consumption was simply the dominate term in the expansion for the practical range of applied voltages to the CMOS devices of historic relevance.

But the third, fourth, and higher order terms were always there, albeit with near-zero coefficients out front so the contribution to the overall power consumption historically had been negligible and one was safe to ignore them (and to teach others to ignore them by way of never mentioning them in the first place).

You've totally lost me. Math/Calculus isn't one of my strong points ^^

Is 0.832v correct, or not?

 

[Idontcare]

Originally posted by: MarcVenice
You've totally lost me. Math/Calculus isn't one of my strong points ^^

Is 0.832v correct, or not?

Oops, sorry, , yes the 0.832v is correct but its only for idle with no load when all the powersavings features are kicked in.

To load it up the Vcc then goes to 1.25v or thereabouts, as expected.

The thing with Coolaler though, and you always must keep this in mind with this guy, is he is THE premier sanctioned leak poster-boy for Intel and has been for as long as I can remember (back to P4 days). What that means is Intel isn't exactly going to hand him run-of-the-mill silicon for him to run off to his forums posting screenies about...think cherry-picked and hand selected, just like Coolaler himself.

So I like the info, its coming just as expected for a Nov release timeframe (it was late July and early August last year when Coolaler was doing the same thing with Nehalem leaks..remember when Francois got his nose out of a joint over NDA violations until someone internal told him to shutup and let the plan play out?) and the good news is that the silicon isn't so unhealthy as to take 1.5V to operate at 4GHz. As for anything chip-specific like Vcc at any GHz, or overclocking capability to XYZ GHz...zero point in any of us getting excited over it.

 

[deputc26]

Thank you IDC, it is interesting that your data fits rather perfectly to the power of 3. I wonder why the dominant term changed from x^2 to x^3 as process tech got better?

MarcVenice .832v was not correct, 1.248v is. Must be a BIOS Bug of some kind that gave the .832v @ 4.0Ghz indication.

 

[MarcVenice]

Originally posted by: Idontcare

Originally posted by: MarcVenice
You've totally lost me. Math/Calculus isn't one of my strong points ^^

Is 0.832v correct, or not?

Oops, sorry, , yes the 0.832v is correct but its only for idle with no load when all the powersavings features are kicked in.

To load it up the Vcc then goes to 1.25v or thereabouts, as expected.

The thing with Coolaler though, and you always must keep this in mind with this guy, is he is THE premier sanctioned leak poster-boy for Intel and has been for as long as I can remember (back to P4 days). What that means is Intel isn't exactly going to hand him run-of-the-mill silicon for him to run off to his forums posting screenies about...think cherry-picked and hand selected, just like Coolaler himself.

So I like the info, its coming just as expected for a Nov release timeframe (it was late July and early August last year when Coolaler was doing the same thing with Nehalem leaks..remember when Francois got his nose out of a joint over NDA violations until someone internal told him to shutup and let the plan play out?) and the good news is that the silicon isn't so unhealthy as to take 1.5V to operate at 4GHz. As for anything chip-specific like Vcc at any GHz, or overclocking capability to XYZ GHz...zero point in any of us getting excited over it.

Thanks for the clarification. I allready saw a p55 + Core i7 870 go up to 4GHz + btw, so I know they can do it, it was at least 3DMark06 stable and on air. It was during the MOA-event from MSI, in Munich, when they showcased the new OC-Genie function. I forgot to snap a picture of the 4GHz part, but I did manage to take a pic when they ran 3DMark 06. Didn't see any voltages btw. http://tweakers.net/ext/i/1247836798.jpeg

As for Francois, I haven't heard many good things about him, don't think many ppl on XS like him very much

 

[Idontcare]

Originally posted by: deputc26
Thank you IDC, it is interesting that your data fits rather perfectly to the power of 3. I wonder why the dominant term changed from x^2 to x^3 as process tech got better?

TBH I think it happened a long time ago (meaning circa 130nm or 180nm nodes) as the gate oxide thickness dropped below ~5nm and the contribution of tunneling leakage to the overall IC's total power consumption began to become >0 and the static leakage component became significantly non-zero.