48 mb cache from IBM

[verndewd]

http://www.eetindia.com/ART_8800453782_...522,8941139293,2007-02-19,EEIOL,EENEWS

IBM Corp. detailed a method for tripling the amount of memory on a microprocessor, potentially doubling its performance. By combining techniques in process and circuit design, IBM believes it can put as much as 48MB of fast DRAM on a reasonably sized CPU when its 45nm technology becomes available in 2008.

IBM's upcoming Power6 CPUs use 8MB SRAM cache. Rival Intel Corp.'s Itanium processors use as much as 18MB.

"Processors are definitely cache starved, and as you go more towards multi-core processors, the need for memory integration becomes more acute," said Subramanian Iyer, a distinguished engineer and director of 45nm technology development at IBM. "There are some server chips that could not be made without this technology," he added.

In a paper at the International Solid State Circuits Conference last Feb. 14, IBM described a 65nm prototype embedded DRAM with a latency of just 1.5ns and a cycle time of 2ns. That's an order of magnitude faster than today's DRAMs and competitive with SRAM that is typically used for microprocessor cache memory.

"To put 24-36MB of memory on a chip, you would need a 600mm² die today. Using this technology you could put that much memory on a 300-350mm² die," Iyer said.

IBM expects to use the technique on its future Power and Cell processors as well as have it available for its ASIC customers. "It's being defined in a way that it can be part of our standard 45nm process technology," Iyer said.

IBM combined two advances to enable the new memory integration. The company found a way to migrate its deep trench technology used for DRAMs from CMOS to its silicon-on-insulator (SOI) logic process. In a paper last December, IBM described that work that involved suppressing the floating-body effect in SOI.

"Our entire processor road map is based on SOI," said Iyer.

New circuit designs use short bit lines to eliminate the need for sense amps that detect voltage differences between the bit lines and a capacitor, a process that makes DRAMs relatively slow. The new design uses a three-transistor micro-sense amp that lets voltage current directly drive transistor gates.

IBM used embedded DRAM in a custom processor designed for its high-end Blue Gene/L supercomputers, but has not been able to use the technology in mass market computer chips to date. "This is 100 per cent mainstream and we expect to get it in products in 2008," Iyer said.

Intel and other chip makers are investigating using the floating body cells to store charge as one alternative for embedded memory. Other chip makers are researching stacking memory and processor dice in multi-chip modules.

Intel archrival Advanced Micro Devices co-develops process technology with IBM and could use the embedded DRAM technology as a way to compete with Intel.

- Rick Merritt
EE Times

 

[Lord Evermore]

Technically "cache starved" isn't possible. Cache is nothing but high speed memory. If main memory was that fast, cache wouldn't be needed. So it's really starved for low-low latency, high bandwidth memory in general. The only reason to call it cache starved is because that's the only type of low latency memory we have.

I know, completely irrelevant and pedantic and foolish.

 

[SickBeast]

This doesn't sound all that revolutionary seeing as intel currently has 18mb of cache on some of its high-end chips. In a year, they probably won't be too far off this 48mb figure.

 

[DrMrLordX]

It is potentially revolutionary though . . . Intel has 18mb of cache on some Itaniums which are HUGE. Tech like this could allow large blocks of l2 on much smaller chips . . . and since this is IBM's own tech, AMD may be able to utilize it when they complete their die shrink to 45nm at about the same time that IBM is planning to do it. This may allow AMD to elegantly incorporate caches as large as 4-8 mb on chips no larger than the ones they sell now.

 

[Lonyo]

Intel are working towards stacked dies with increasing amounts of DRAM on chips anyway though, AFAIK.
See here: http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2925

Obviously there will still be a need for main memory, as Intel is currently estimating that a single layer could house 256MB of memory. With a handful of layers, and a reasonably wide external memory bus, keeping a CPU with tens of cores fed with data now enters the realm of possibility.

 

[Sunner]

Originally posted by: SickBeast
This doesn't sound all that revolutionary seeing as intel currently has 18mb of cache on some of its high-end chips. In a year, they probably won't be too far off this 48mb figure.

Thing about this is that it's eDRAM instead of SRAM.
SRAM takes up far more die space than DRAM, 6 transistors per cell as opposed to 1 for DRAM I believe(feel free to correct me here).
Montecito packs a lot of SRAM on the die, and correspondingly the die is huge, sitting at 600 mm2 or so.

 

[verndewd]

Originally posted by: Lonyo
Intel are working towards stacked dies with increasing amounts of DRAM on chips anyway though, AFAIK.
See here: http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=2925

Obviously there will still be a need for main memory, as Intel is currently estimating that a single layer could house 256MB of memory. With a handful of layers, and a reasonably wide external memory bus, keeping a CPU with tens of cores fed with data now enters the realm of possibility.

Intel is planning agressively on cache as well. One unsubstantiated claim was 48mb by 09.The poster did not provide a link. What I find interesting is that prior to this new developement zram was 1.5-2x more dense . And I think it is good news for AMD as a dev partner I would imagine this could make it into a K10 stepping given their modular manufacturing push.

I really have my fingers crossed for the playing field to even out some in tech with amd and intel.