VladTrishkin
Senior member
Ace Reports:
<< Samsung also fattens DRAM densities with a 4-Gbit double-data-rate SDRAM. The architecture eschews the 0.14-micron technology node used for 1-Gbit devices in favor of 0.10-micron CMOS to realize a 0.10-micron2 cell. Samsung researchers used gain-controlled pre-sensing and active calibration of bit-line reference voltages to improve sensing margins. The company said the design is the first time 4 billion transistors have been contained on a single IC.
Intel will present two papers detailing its recent innovations in both the IA-32 and IA-64 segments. Attacking low-power/high-performance dilemmas for handheld applications, Intel will describe an enhancement to the IA-32 architecture that offers up to 1,000-Mips performance at 800 MHz but runs at operating voltages of 0.7 to 1.65 V.
Intel engineers also will describe a 4-GHz integer execution unit deployed in 0.18-micron CMOS. The design, which runs the ALU at twice the frequency of the rest of the processor to reduce latency, is designed to boost desktop and server speeds while retaining instruction-set compatibility. Circuit techniques that Intel deployed in an implementation of the ARMv5TE allow power and performance to be widely adjusted for use in mobile devices. The device, to be described at the conference, is a 16.77-mm2 hard macro intended for use in system-on-chip (SoC) designs.
At the IA-64 level, Intel bumps up by 1.5 times the frequency of its current 64-bit processor in a 1.2-GHz design that exploits 3.3 Mbytes of on-die cache, organized among four separate arrays in a three-level hierarchy. The lowest levels of cache achieve a low enough access time to enable zero-penalty access for integer instructions, Intel will report. Engineers from Compaq Computer Corp. are keeping pace on the high end with a 1.2-GHz Alpha processor that claims a 44.8-Gbyte/s chip-pin bandwidth. The design incorporates a 1.75-Mbyte L2 on-chip cache.
Sun Microsystems Inc. will describe a version of its MAJC processor, including two complete four-way-issue VLIW processors running at 500 MHz. And IBM Corp. will describe a Power4 processor running at more than 1 GHz with two four-way out-of-order-issue processors. >>
-Intel is gaining speed, 2Ghz is not that far away now..
<< Samsung also fattens DRAM densities with a 4-Gbit double-data-rate SDRAM. The architecture eschews the 0.14-micron technology node used for 1-Gbit devices in favor of 0.10-micron CMOS to realize a 0.10-micron2 cell. Samsung researchers used gain-controlled pre-sensing and active calibration of bit-line reference voltages to improve sensing margins. The company said the design is the first time 4 billion transistors have been contained on a single IC.
Intel will present two papers detailing its recent innovations in both the IA-32 and IA-64 segments. Attacking low-power/high-performance dilemmas for handheld applications, Intel will describe an enhancement to the IA-32 architecture that offers up to 1,000-Mips performance at 800 MHz but runs at operating voltages of 0.7 to 1.65 V.
Intel engineers also will describe a 4-GHz integer execution unit deployed in 0.18-micron CMOS. The design, which runs the ALU at twice the frequency of the rest of the processor to reduce latency, is designed to boost desktop and server speeds while retaining instruction-set compatibility. Circuit techniques that Intel deployed in an implementation of the ARMv5TE allow power and performance to be widely adjusted for use in mobile devices. The device, to be described at the conference, is a 16.77-mm2 hard macro intended for use in system-on-chip (SoC) designs.
At the IA-64 level, Intel bumps up by 1.5 times the frequency of its current 64-bit processor in a 1.2-GHz design that exploits 3.3 Mbytes of on-die cache, organized among four separate arrays in a three-level hierarchy. The lowest levels of cache achieve a low enough access time to enable zero-penalty access for integer instructions, Intel will report. Engineers from Compaq Computer Corp. are keeping pace on the high end with a 1.2-GHz Alpha processor that claims a 44.8-Gbyte/s chip-pin bandwidth. The design incorporates a 1.75-Mbyte L2 on-chip cache.
Sun Microsystems Inc. will describe a version of its MAJC processor, including two complete four-way-issue VLIW processors running at 500 MHz. And IBM Corp. will describe a Power4 processor running at more than 1 GHz with two four-way out-of-order-issue processors. >>
-Intel is gaining speed, 2Ghz is not that far away now..
