3ns RAM really 3ns?

[scaryjeff]

Does the kind of RAM used on graphics card boards really have 3ns RAM? What I mean is, can you ask the memory for any random address, and the memory will have the data ready 3ns later, or does the 3ns figure only correspond to the reading of sequential locations?

 

[Peter]

No. The 3ns is the maximum clock rate. There's a shedload of row and column addressing overhead in front of a data transfer, typically something around 11 clocks. When this is done, DDR RAM will start shovelling data at a rate of one every half clock - as long as the chipset maintains the burst access.

 

[scaryjeff]

I see. One of my lecturers is working on a gigasample/second system for wave height analysis or something, and I thought perhaps the kind of memory used in video cards would be suitable. Oh well, thankyou - and sorry if this isn't technical enough for this forum.

 

[rjain]

You should read some of the DRAM overviews on this site, aceshardware.com, and arstechnica.com if you're interested in the details of what those delays are. Those "2-2-2-6" numbers you see are the number of (in this case 3ns) clock cycles for each of those delays.

 

[Peter]

scaryjeff, you'll need to make your RAM array wider if you can't make it faster. Guess what those dual channel mainboards and 256-bit-bus graphics cards are after ...

 

[f95toli]

I few weeks ago I meet guy who was working on a pattern generator that was suppose to work at around 30 GB/s (I think, it might have been faster). It basically was a card with some type of memory, first you wrote the pattern to memory and then you could somehow "dump" the whole content of the memory at once (I should point out that this was not a DIY project, he works at a research institute). Unfortunately I forgot to ask him what kind of memory he was using, I do remember it was commercialy available.

 

[ZeroNine8]

if you could dump different parts of it to multiple memory modules, you could achieve a transfer speed greater than that of the individual modules (if you do it right).

 

[scaryjeff]

Yeah that's a good idea. He said they are currently using some commercially available 'card' that does the job, but he said it costs something like £20,000 - I'm not sure of the details because this isn't a project I am working on (we just did a simple circuit to generate the laser pattern).

 

[uart]

or does the 3ns figure only correspond to the reading of sequential locations?

Yes that is correct, after the initial latency you can theoretically achieve once byte/word (etc dedending on the data width) every 3 ns.


If I may just add a quick question of my own here for everyone. Can you remember when we used the older styles of ram (like EDO for example) and I think the fastest that was commonly available was about 60ns. Then SDRAM came out and in the blink of an eye "typical" RAM specs had suddenly dropped to 10 ns. Did this correspond to a change from specifying "total access time" to specifying only clock speed (synchronous) or was there something else involved here ?

 

[scaryjeff]

At a guess that was when they implemented special methods for obtaining many sequential addresses in a row giving a short access time for those sequential reads, but as I say, that's only a guess.

 

[Peter]

The switch from async to sync technology indeed brought burst throughput way down. Btw, 3-ns DDR RAM transports data every 1.5 ns - that's what DDR technology is about. The row and column addressing still works at the same speed as with SDR RAM - and that's why saying DDR RAM is twice as fast is pure nonsense. It isn't. Could the marketing folks please stop doubling the MHz figures for DDR stuff?

E.g. a typical burst transfer in an x86 PC consists of addressing followed by 8 sets of data. On SDR RAM, let's say it is 11+8=19 cycles, with DDR it's down to 11+4=15. That's just a mere 45 percent faster, not twice as fast.