3D NAND, SMLC, and trends in density

[Idontcare]

3D NAND memory cell technology

http://translate.google.com/tr...&tl=en&history_state0=

It's google translated (so the words make little sense) but there are lots of graphics that are easy to interpret. Pretty cool stuff.

 

[Idontcare]

Goto-san has released some more info on upcoming 3-bit and 4-bit MLC's.

http://translate.google.com/tr...&tl=en&history_state0=

A few highlights - here's some direct die-size comparisons between increasing density by increasing IC size versus increasing density by increasing bit-count per cell all at the same technology node.

http://pc.watch.impress.co.jp/.../html/kaigai9.jpg.html

Pretty cool IMO. The X3 reduced the IC size by 22% (182mm^2 -> 142.5mm^2)...actually a somewhat lackluster reduction given that the opportunity with X3 is to shrink by 33% (121.3mm^2 would be a linear reduction, i.e. a linear scaling of the bit density in going X2 -> X3).

Nevertheless it underscores the fact that increasing IC complexity comes at a cost of increasing the bit storage structures themselves in order to manage the necessity of distinguishing between 8 charge levels for encoding the 3-bits that can be programmed into an X3 device.

Also of no surprise, but is nice to have official confirmation of our expectations, this Samsung slide details the order-of-magnitude loss of write endurance (lifetime) and performance (speed) with the X3 chips versus 2-bit MLC.

Write endurance drops to a dismal ~1k writes for the X3...we aren't likely to be seeing any SSD devices created with X3 or X4 flash anytime soon. Of course the write endurance can be improved by increasing the size of the bit structures, but that defeats the purpose/advantage (bit density) of going X3 versus 2-bit MLC in the first place.