Graysky, I would recommend trying a thicker based paste since the high temps might make the TIM flow over a period of time. I am not sure if thats possible to happen but ferzerp was speculating such earlier. Maybe he will chime in soon.
BonzaiDuck
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BonzaiDuck
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Your point being?
Just for levity, I'm wondering if we have some sort of telepathic communication occurring here. I found that earlier thread in its entirety and looked at it about the time you posted this link . . .
But is abrasive and not good for a CPU die
I mean really, I guess if you are careful enough IC diamond or Antec formula 7 wouldn't hurt.
BonzaiDuck
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But is abrasive and not good for a CPU die
The particulate has a maximum size of 40 microns. Some diamond powder I bought to make my own paste -- as I remember -- was supposed to have a size of between 2 and 5 microns, IF I am not mistaken. If I were going to use it, I'd apply it to the IHS and then apply the IHS to the die. The particles are not going to move around -- and as I said, as the paste dries out, it feels and looks like gray rubber.
If somebody thinks that the silicon surface of the die is too fragile for this, you should say so, but I just can't imagine doing harm with it. if it is a risk, then the better option in any event as far as thermal conductivity/resistance is something like Liquid Ultra.
EDIT: 40 microns can't be right -- I got that from the spec summary of IC Diamond at www.frozencpu.com. I'll bet they meant 4 microns.
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BonzaiDuck
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We've got more than a couple threads following this parallel topic, and personally I find no problem with that.
There are various issues with the "direct application" -- pressure, risk to the die itself, and so on.
Right now, we're also looking at the IHS and the adhesive, which seems to have a uniform thickness, and I posed the possibility that the entire combination of materials was supposed to stabilize the IHS or support it so that any additional pressure on the die did not put it at risk. So if some might worry about nano-diamond particles and what they might do to silicon, I'd worry about cleaning off the IHS adhesive and/or sanding down the flange or edge of the IHS.
Somebody is going to bear the full cost of uncalculated risks for these experiments, and it's probably a good idea to get them all out on the table for discussion.
My hypothesis is that when the caulk is removed (black dots) the headroom above the die (red arrows) decreases by that same distance. So if you lap the bottom of the IHS, you will decrease further the internal headroom perhaps to the point of crushing the die when locked in place. Just my thought. Others?
BonzaiDuck
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My hypothesis is that when the caulk is removed (black dots) the headroom above the die (red arrows) decreases by that same distance. So if you lap the bottom of the IHS, you will decrease further the internal headroom perhaps to the point of crushing the die when locked in place. Just my thought. Others?
As I said in the parallel thread to this one -- Yeah -- I agree. Also, to this point, nobody has responded to the issue as to whether micronized diamond particles < 4micron in size would have any deleterious effect on the silicon surface. Many of the TIM pastes rely on particulate substances, but none that hard. So I might wonder how thick is the silicon between the "CPU" part and the IHS. What, besides pressure, might damage it? Or, how might conductive material like "Liquid Ultra" create any hazard to the chip? What's to prevent using a "superior" TIM as opposed to a "better" one?
Addendum: If people wanted to eliminate the IHS altogether and still use the IHS to support a heatsink-base under pressure, they might grind off the top of the cap to the point where the top surface is removed, leaving the sides and flare of the cap to support the HSF assembly. I'd seen cases where people had done this with other processors, sanding off just enough of the IHS to expose the die underneath.
But we're looking for simple, safe solutions that don't create risks or don't particularly require tremendous precision.
ADDENDUM: I don't see any problem with using conductive TIM -- from the pictures I've seen of the die from Maximum PC courtesy of some Japanese outfit named "PC Watch." The latter reported a drop from 84C to 69C with Liquid Pro with an OC of 4.6 Ghz @ 1.2V.
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I updated the first post of this thread with new results having lapped both the IHS and the base of the heatsink. They start under the section entitled, "Part 2."
I was able to drop my vcore offset from +200 mV down 150 mV to +5 mV and have a stable system as evaluated by: 5 h of mprime large/FFTs, 2 h of continuous compiling, 2 h of systest 64M, and 2 h of linpack+gcc. Lower operating temps have their tangibles. This is @ 45x100. I'll now switch over to 47x100 to see if I can drop the vcore by a proportional amount and might try 48x100. Just wanted to update.
ShintaiDK
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My hypothesis is that when the caulk is removed (black dots) the headroom above the die (red arrows) decreases by that same distance. So if you lap the bottom of the IHS, you will decrease further the internal headroom perhaps to the point of crushing the die when locked in place. Just my thought. Others?
I agree. I had the same thoughts. The distance really matters alot in terms of heat transfer.
BonzaiDuck
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The more attention you give to reducing the clearance, the more precise must be the work.
ShintaiDK
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Yep, I also guess thats why the clearence is relatively high. So it can be applied this way in millions and quickly. Not to mention work everywhere, anytime, all the time.
BonzaiDuck
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Thing is -- has anyone attempted to measure any "clearance?" You'd think that their production line would drop a bead of rubber adhesive on the board or heatspreader, mate the two, and the clearance would still be minimal. Once the rubber sets or hardens, you'd think that's as close as it would get.
I think IDC had used his calipers or a micrometer to gauge the thickness of the adhesive and the dimensions of the processor cap. I can't recall if he uncovered a "gap" between the processor and lid.
That's why I was skeptical about removing the adhesive. Pictures of the separated IHS and processor/circuit-board before removal of the TIM makes it look as though the two surfaces had made full contact.
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Avalon
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Interestingly, the lower offset (-150 mV) only translated into -1C drop across cores:
Squares are the offset of +0.020 V and circles are the offset of +0.005 V.
Here are a few visuals on the VID distributions. Remember, my script is sampling 30 times/sec and that on day 4, I dropped the offset by -150 mV:
Here it is in terms of raw counts:
Squares are the offset of +0.020 V and circles are the offset of +0.005 V.
Here are a few visuals on the VID distributions. Remember, my script is sampling 30 times/sec and that on day 4, I dropped the offset by -150 mV:
Here it is in terms of raw counts:
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