Originally posted by: deputc26
". Intel also reported the smallest contacted gate pitch to date, 112.5nm, ahead of competing 32nm processes and TSMC?s 28nm process." I really wish these companies wouldn't cheat on node labels, clearly TSMC's "28nm" process should be called a 32nm process, though I suppose SRAM cell size falls into the former category...
Also given Intel's 32nm contacted gate pitch of 112.5nm and IBM's 32nm contacted gate pitch of 126nm. Is it safe to assume that even on the same advertised node Intel will have a 126^2/112.5^2 = 25% advantage in areal density over IBM/AMD. I understand it's not that simple but I also believe contacted gate pitch is the best indication areal density. Also 126nm was for IBM's bulk process, for their SOI process contacted gate pitch is 130nm widening the theoretical gap to 33.5%.
It's not really cheating, there is no legal or technical definition of the term "node". The fact that anyone can call any node they want as anything they want is entirely true.
But it isn't so different in other industries. Go to home depot and buy a 2x4 wood board, it won't measure out to be 2inches by 4inches even though it is labeled as being a 2"x4" board on the sticker that hangs in front of the wood pile.
Likewise on the auto industry. You don't have to wait until 2010 to buy the new 2010 Toyota Camry. And come 2011 you will still be able to buy brand new 2010 Toyota Camry. And just because one car manufacturer calls their car a 2010 model doesn't mean it compares in any way, shape or form with another car manufacturer's 2010 model.
But that isn't to say that these process technology guys aren't abusing ever-so-slightly the node labels given that they clearly understand the market connotations of the nodes themselves being late to market relative to their competition.
As for the specifics of the numbers, the math you are looking into regarding areal densities and so on based on contacted pitches and sram...it is extremely difficult to reduce the metrics of performance for a transistor down to simple enough terms with which you could then make meaningful comparisons.
Smaller sram doesn't mean much if it also can't be clocked as high as needed or if it is so small that it actually is on the verge of being unmanufacturable from a process-control standpoint and as such the yields end up being abysmal.
There are tradeoffs that go into every single metric of success for an IC, from design thru process tech. Which is in large part the reason why no two companies have identical specs for their transistors at the same node regardless the timeline delta between the release of those nodes.
For 22nm for example the Ivy Bridge and Haswell design teams are making requests to the Intel 22nm development team to deliver certain performance specs that will enable them to design features into their products that the AMD designers working on 22nm BD shrink (whatever it is called internally) simply don't need or require the GF 22nm development engineers to develop and deliver.
That doesn't mean GF's 22nm is less than Intel's, it just means it will be optimized with a set of different constraints in place versus the constraints in place around the optimization of Intel's 22nm process tech.
At the end of the day what matters to us, and to the chip makers too, is that when we go to newegg to buy a cpu come Dec 2011 that both Intel and AMD have 22nm cpu's available and shipping and that each performance class has a competitor.
We don't want to see 22nm Ivy Bridge owning the high-end performance market for a year before AMD releases their 22nm competitor, and we don't want to see GF's release 22nm node at the same time as Intel only to find out that the resultant products are so slow that they only compete with the mid to low-end range of Intel's offerings at the time.
The areal density advantages really only matter in those cases where "all else is equal"...as then areal advantage translates into cost advantage (smaller die, higher yield, lower cost) or can be leveraged into a performance advantage (same size die, same size yield, more sram cache, higher performance).
But if you have an areal advantage that comes only with a distinct performance disadvantage (low clockspeeds) or a distinct manufacturing disadvantage (high level of litho reworks, increases cost - or higher level of parametric yield loss due to process variability) then one would hope you did that on purpose because you intend to fabricate IC's that are going to compete in a marketspace where high performance is not a gross-margins enabler (such as the mobile phone market).
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