hey guys - looking for an in depth explanation of amd architecture and how what exactly is going 2 ghz. and how the bandwidth below is determined.
basically how they get these numbers, for dual channel ddr 400 ram.
http://www.amd.com/us-en/Processors/Pro...ion/0,,30_118_9485_13041^13043,00.html
HyperTransport? technology for high speed I/O communication
One 16-bit link at 2000MHz
8 GB/s HyperTransport? technology I/O bandwidth
14.4 GB/s total delivered processor-to-system bandwidth
here are my numbers, incorrect assumptions yet hopefully correct math:
A:
pc3200 ddr400 3.2gB
pc4000 ddr500 4.0gB
100 mhz ddr = .8gB of memory bandwidth
200 million cycles = .8gB
200000000 cycles = 6710886.4 bits (.8 * 8 * 2^(10*2))
1 cycle = 0.033554432 bits transferred
shouldn't this be something like 32 bits transferred per cycle?
B:
One 16-bit link at 2000MHz
8 GB/s HyperTransport? technology I/O bandwidth
14.4 GB/s total delivered processor-to-system bandwidth
100mhz ddr = .8gB
1000mhz ddr = 2000mhz = (10*100mhz) ddr = 8gB - from hypertransport - what exactly is this, what is this connecting? seems to have nothing to do with the memory bus;
14.4gB - 8gB = 6.4gB;
two channels for memory; 6.4/2 = 3.2gB per channel = bandwidth of pc3200 400mhz ddr ram. so what exactly is this HT area doing?
thanks for any help in my understanding !
basically how they get these numbers, for dual channel ddr 400 ram.
http://www.amd.com/us-en/Processors/Pro...ion/0,,30_118_9485_13041^13043,00.html
HyperTransport? technology for high speed I/O communication
One 16-bit link at 2000MHz
8 GB/s HyperTransport? technology I/O bandwidth
14.4 GB/s total delivered processor-to-system bandwidth
here are my numbers, incorrect assumptions yet hopefully correct math:
A:
pc3200 ddr400 3.2gB
pc4000 ddr500 4.0gB
100 mhz ddr = .8gB of memory bandwidth
200 million cycles = .8gB
200000000 cycles = 6710886.4 bits (.8 * 8 * 2^(10*2))
1 cycle = 0.033554432 bits transferred
shouldn't this be something like 32 bits transferred per cycle?
B:
One 16-bit link at 2000MHz
8 GB/s HyperTransport? technology I/O bandwidth
14.4 GB/s total delivered processor-to-system bandwidth
100mhz ddr = .8gB
1000mhz ddr = 2000mhz = (10*100mhz) ddr = 8gB - from hypertransport - what exactly is this, what is this connecting? seems to have nothing to do with the memory bus;
14.4gB - 8gB = 6.4gB;
two channels for memory; 6.4/2 = 3.2gB per channel = bandwidth of pc3200 400mhz ddr ram. so what exactly is this HT area doing?
thanks for any help in my understanding !