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2.4C SL6Z3..... EE In 2.4C Clothing?

T

Technonut

Diamond Member
I have been reading This Thread that shows the IHS removed (horrible results :Q ) from a 2.4C SL6Z3.

I have not seen this discussed here. Any thoughts?.. opinions? Perhaps one of our resident Intel experts (Hint Hint) could shed some light... 😉
 
I don't know what was more horrible, the results or the actual photography. That picture was hideous. Maybe a camera resolution issue. Someone near the bottom declared it an "EE" core by virtue of the aspect ratio of the sides. Like a Barton compared to an XP, it is more rectangular.

What I want to know is what did they attach that IHS thing with?

The irony of it all is that the guy never got to fire it up.
 
Hehe... It was probably the "GOD" of all chips too. Likely would have done 4.5 at default vcore or something...

ANyways, they sure look like EE chips, but I am not gonna ruin mine just to find out!

PJ
 
The SL6Z3 appears to have the same capacitor layout as the EE also.... Some sort of strong thermal adhesive must have been used to stick to the IHS like that... Perhaps to enhance thermal transfer???

The irony of it all is that the guy never got to fire it up
Click to expand...
It is a shame, but makes for interesting assumptions....
 
Originally posted by: THUGSROOK
i read something somewhere....

that all new P4 chips will be using the "EE" configuration to save $.
Click to expand...

This would not save money, the die size would be a massive cost increase. We arent talking an extra 256k of cache, its 2MB of L3.

However i could see them taking the "Celeron approach" and disabling the L3 on defective EEs.
 
no ~ not the EE cache.
im talking about the chips "config".
less tooling if they are all the same.

it will also lower the price of P4 considerably during the next 6 months.
 
I can't tell by that pic... He destroyed the silicon!!!

But no... There's no way that Intel is remarking the EE's as regular P4's. No way.
 
Originally posted by: Wingznut
I can't tell by that pic... He destroyed the silicon!!!

But no... There's no way that Intel is remarking the EE's as regular P4's. No way.
Click to expand...
Ahh.. There you are... I was hoping that you would show up. 🙂

Yes, I have not seen a processor so butchered from removing the IHS before.. Can you comment on whether a new thermal adhesive is being used? If the core size is larger as indicated (somewhat) by the picture, is this just the M0 revision design, and why is it larger?

Inquiring minds want to know..... 😉

 
I have no idea regarding the details about packaging... And since I don't really know what he has (or what it really was), your speculation is as good as mine. It's just way too fubar'd to say what it is/was.

Now that I think about it, I suppose it is possible that the Gallatin die had enough defective cache that it couldn't be a P4EE... And selling it as a P4c would obviously be better than throwing it away. But I really couldn't say for sure.
 
Interesting follow-up from an Intel Datasheet... Here

"Intel Pentium(R) 4 processor with 512KB L2 cache on .13 Micron Process M-0 stepping is a unique stepping of Intel Pentium(R) 4 processors. The currently shipping Intel Pentium(R) 4 processor with 512KB L2 cache on .13 Micron Process D-1 stepping will continue to ship in high volume into the future with no plans for conversion to M0 stepping."
Click to expand...



 
Originally posted by: Technonut
Interesting follow-up from an Intel Datasheet... Here

"Intel Pentium(R) 4 processor with 512KB L2 cache on .13 Micron Process M-0 stepping is a unique stepping of Intel Pentium(R) 4 processors. The currently shipping Intel Pentium(R) 4 processor with 512KB L2 cache on .13 Micron Process D-1 stepping will continue to ship in high volume into the future with no plans for conversion to M0 stepping."
Click to expand...
Click to expand...

If that is the case, then these M0s must be "binned" XEs (Extreme Editions).
 
Originally posted by: Thor86

If that is the case, then these M0s must be "binned" XEs (Extreme Editions).
Click to expand...

Seems about right. There was an announcement in August (I think) saying that the M0 stepping on 2.4Cs would be coming out Sept 1st. Maybe the M0 stepping is a "binned" EE. The EE was "released" only a few weeks later.
 
So the question is really what kind of enhancement is the M0 stepping....It seems to be going good for many I have seen overclocking many hitting 3.5ghz to 3.6+ghz.....

However since they are making 3.2ghz EE's and 3.2ghz p4c's then is really the stepping related to the obvious changes associated with making room for the l3 cache??? Can the d1's be as good as the m0 stepping chips???

Who knows I just wonder if it is an EE would the changes be more benficial to higher clocking and if so why....
 
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