133mhz mem clock unstable on MSI 6309

[moocat]

I have a cel2 566@850 and a 128mb stick of generic pc133 (3-2-2). The system is stable with the mem bus set to 100mhz cas2 but becomes unstable with the mem bus at 133mhz cas3. It doesn't run when using the 'by SPD' setting in bios either.

Is there a problem with the VIA 133a chipset, is it specific to the MSI 6309, or do I have a crappy stick of memory?

 

[dakost]

If what you're saying is that your pc 133 memory can run at host clock - 33 while it will not run at host clock at 133 i'd say there is a problem with the memory. Unless the particulat MSI 6309 is a defective motherboard. Or the MSI 6309 doesn't like the oarticular generic memory you have.
I think http://firingsquad.gamers.com/ took the MSI 6309 at 150 in their review. And there is certainly no issue with either the MSI 6309 or the via apollo 133a with 133fsb. Can't you borrow a stick of different sdram from a friend and try it out ?

 

[moocat]

What I'm trying to do is run 'host clock + 33'. I'm not even sure if it is supposed to do that. I've seen others post about having that option with the 133a chipset on the Asus P3VX boards. It seems to be giving me that option on this board but it isn't stable.

 

[Jhhnn]

The 6309 is an unusual board because of the amibios. Mine runs best in spd with a 550e, mushkin athlon memory, fsb 143. I would suggest that you may have a bios compatibility problem with the celeron (new version 1.5 is available, haven't tried it)or a problem with the memory. I'm surprised it won't work in spd, does that generic ram have a spd eeprom? some doesn't.

 

[moocat]

Yea it looks like it has the eeprom (8 pin IC). I'm not sure who made the pcb but the dram is Toshiba 7.5ns...also, I already flashed to bios rev 1.5. I don't really have another stick of pc133 and I don't have another system that I can run the mem clock up to 133mhz.

 

[Jhhnn]

a truly strange problem, enabling spd on this board is generally the holy grail for memory problems. Do you have access to a p3e to try? This would tell if it is the memory or abios problem. What you are trying to do is new and unusual, and perfectly logical for a celeron2. My own experience is limited to the p3e, as is virtually everybody else's. Running the memory at +33 of fsb is a ticket to disaster in that overclocking scenario. I have a hunch that it is a bios problem, but you will have to be able to switch parts to find out. You might contact msi, it may be a known glitch. I'll try your settings on mysystem and post the results, if I can get it to boot at all! EDIT Set my board to 100 fsb, 133 memory speed, spd disabled, and it is working fine as I peck away. Have you tried disabling clkgen spread spectrum in hardware monitor setup? Now I'm grasping at straws. Post back when you find any answers, please.

 

[moocat]

I do have spread spectrum disabled. I'll post if I find out anything new.

Thanks.

 

[moocat]

I tried the 'spd' setting enabled again and then switched the "cpu in Order Queue" setting from '4-level' to '1-level'. It has been running Prime torture test and Final Reality for the past 3 hours. Previously FR or 3DM2K would fail after a several minutes even without Prime running in the background.

Can someone clarify what the '4/1-level cpu in order queue' setting is doing exactly? Should I beable to run it with it set to '4-level'?

 

[dakost]

In general when one uses 100 fsb on an apollo 133a and one selects host clock + 33 it should work as long as the memory is pc 133 or pc 100 capable to run at 133 MHz.
I'm not sure what exacly 4/1-level cpu in order queue does, but in terms of performance it dramatically increases memory throughput if it is set to 4. I think that anatech has it mentioned in some of his reports. And on Hard OCP when they tested the Soyo 7VCA. My personal experience is that it improves memory throughput by about 25% and that on an MSI 6199VA apollo 133 (not a) motherboard. I also recall that in a review and i don't remember exactly which review, that it may be unstable to use the setting of 4. Although i have seen numerous apollo 133a reviews in which it is set to 4 with no problems. Actually, there are apollo 133a motherboards which do not include the option to set 4/1-level cpu in order queue in which case, one can use Oda's tweak
utility to set it along with other memory parameters ...
http://www.viahardware.com/memorytweak.htm
You can obviously try and set it to 1 and see whether it will make your memory stability go away. But that will decrease performance.
You can try these sites to see the reviews and the set up they used
http://www.hothardware.com/hh_files/Motherboards/MS-6309.htm
http://sysopt.earthweb.com/reviews/msi6309/index.html
http://firingsquad.gamers.com/hardware/6309/page6.asp
Hothardware reports that they couldn't run above 143 with a cpu that was able to run at higher speeds while difingsquad reports that the cpu they tested on the 6309 reached 146 fsb, the same as in other mobo's. I hope this helps.

 

[Pennstate]

You can't enable spd with the +33 setting unless you have the 1.5 bios. That's what did it for me and somebody else.

 

[moocat]

I have the 1.5 bios. If I set the IOQ setting to 4-level it won't even boot.

So, what is faster...IOQ 4-level w/ 100mhz mem clock, cas2 ...or...
IOQ 1-level w/133mhz mem clock, cas2?

 

[Jhhnn]

Glad to see that you are getting this sorted out, I probably would not even have tried changing that 4/1 setting, myself. What Dakost posted is pretty much the way I remember it, but couldn't recall any specifics. Which way is faster? dunno, but maybe final reality will tell the story, or some other benchmarking program. I'm hooked on this story, sure want to find out how it ends.

 

[moocat]

I don't have alot of free time to experiment with this. I really would like to confirm that it will run IOQ 4-level with the host clock at 133mhz. I'm hoping that getting rid of the asyncronous mem bus clock will cure the problem.

I don't know anything specific about the function of the memory controller but I'm guessing that to run a mem clock faster than the host clock would require some sort of data buffer. Perhaps IOQ 4-level causes this buffer to be 'over-run'.

There has to be someone here that has some in depth knowledge of the functionality of the VIA chipset.

Could someone send me a P3700e to test for a few months ;-)