1000 core cpu

[Modelworks]

Interesting read of using FPGA to create 1000 smaller cores then use that as a processor unit.

Speed of 20x that of the current desktop cpu is very impressive. I just want to see the actual code and methods because DSP can also do this and I hope that their processor isn't working the same way but is more generalized.



http://news.techworld.com/personal-tech/3254758/scottish-researchers-claim-1000-core-processor/

Researchers at a Scottish claim to have made a breakthrough in the drive towards more powerful processors while conserving energy too. The team, from Glasgow University, led by Dr Wim Vanderbauwhede, have succeeded in squeezing 1,000 cores on a single chip.
The researchers, working in conjunction with colleagues from University of Massachusetts, Lowell, used a chip called a Field Programmable Gate Array (FPGA) which can be configured into specific circuits by the user rather than relying on the factory settings. This technology allowed Dr Vanderbauwhede to divide up the transistors within the chip into small groups and ask each to perform a different task thus creating a 1,000 mini-circuits – or to put it another way, creating a 1,000-core processor.
To demonstrate the chip's effectiveness, the research team used it to process an MPEG algorithm at a speed of 5Gbps, about 20 times faster than processors used in current PCs.
Dr Vanderbauwhede, who hopes to present his research at the International Symposium on Applied Reconfigurable Computing in March, said: "FPGAs are not used within standard computers because they are fairly difficult to program, but their processing power is huge while their energy consumption is very small because they are so much quicker – so they are also a greener option.
However, he warned that the research was an early proof-of-concept work but added that he hoped "to demonstrate a convenient way to program FPGAs so that their potential to provide very fast processing power could be used much more widely in future computing and electronics."

 

[CycloWizard]

FPGA is used for high-speed control systems because it basically moves the computation from software to hardware. The barrier is programming the unit in a manner which is as flexible as a current CPU so it can be used for lots of applications. I don't know what the timescale is for switching the "program" in the FPGA, but it would have to be pretty fast for it to be really useful for a standard multi-tasking Windows desktop.

 

[esun]

There are many companies that have C to VHDL workflows that use a subset of C and can compile a bitfile out of it. However, performance tends to be much worse than hand-written VHDL (as you'd expect), although the decrease in development time can be massive. Reprogramming an FPGA is pretty fast, on the order of 1 ms IIRC. However, modern designs allow dynamic partial reconfiguration in which you can reconfigure one part of the FPGA while the rest continues to run. The less you reconfigure the faster it is, so you could swap out one section in a few microseconds while the rest of the chip keeps running. Coding this up though is non-trivial and the design flow is pretty tedious.

It's not clear to me what those "cores" actually are in the article (and I don't have the time to read all of the author's papers). From the description I'd doubt they are DSP elements, since they are described as processing units akin to a general purpose processor. Perhaps they are very reduced instruction set general-purpose processors with a very small datapath. Not sure how many could fit on a big Virtex-6 (if that's even what they used). Though if they used multiple FPGAs then who knows what the design is.

 

[TuxDave]

There are many companies that have C to VHDL workflows that use a subset of C and can compile a bitfile out of it. However, performance tends to be much worse than hand-written VHDL (as you'd expect), although the decrease in development time can be massive. Reprogramming an FPGA is pretty fast, on the order of 1 ms IIRC. However, modern designs allow dynamic partial reconfiguration in which you can reconfigure one part of the FPGA while the rest continues to run. The less you reconfigure the faster it is, so you could swap out one section in a few microseconds while the rest of the chip keeps running. Coding this up though is non-trivial and the design flow is pretty tedious.

It's not clear to me what those "cores" actually are in the article (and I don't have the time to read all of the author's papers). From the description I'd doubt they are DSP elements, since they are described as processing units akin to a general purpose processor. Perhaps they are very reduced instruction set general-purpose processors with a very small datapath. Not sure how many could fit on a big Virtex-6 (if that's even what they used). Though if they used multiple FPGAs then who knows what the design is.

1ms? Isn't there any synthesis or compile time prior to reprogramming the hardware?

 

[esun]

1ms? Isn't there any synthesis or compile time prior to reprogramming the hardware?

I'm talking about loading a bitfile that you have already built. Building and loading a custom application from VHDL source on the fly would not be possible at this stage (well, not without a LOT of latency).