http://xbitlabs.com/news/story.html?id=1013575024
As our sources in AMD have reported, the closest partners of the company have already received the first samples of the ClawHammer processor for the uni-processor stepping A0 systems made with the 0.13-micron technology in Dresden. Thus, the introduction of x86-64 technology goes as scheduled: AMD was going to start ClawHammer sampling in the first half-year. The first ClawHammer release in the desktop variant is scheduled to the fourth quarter of this year, and there?s no reason to doubt the reality of these plans. Also, the first ClawHammer samples are reported to be showcased at CeBIT show, which is held in the middle of March in Hanover.
We shall remind, that AMD will introduce a number of improvements in Hammer directed both to support the 64-bit code, and to improve the performance. 8 additional SSE registers and 8 general-purpose registers will be added in Hammer. Simultaneously, all general-purpose registers will be extended to 64 bits. Also, AMD brings out support for SSE2 instructions system and improves prefetching algorithms. The processor will have an integer pipeline lengthened up to 12 stages and 17-stage FPU pipeline, with good scalability for further frequency increase. Also, the CPU will have a built-in one- or two-channel memory controller supporting PC2700 DDR SDRAM.
Thanks to NFS4 for the heads up.
EDIT: As I thought, AMD is further ahead with ClawHammer than just "first silicon."
As our sources in AMD have reported, the closest partners of the company have already received the first samples of the ClawHammer processor for the uni-processor stepping A0 systems made with the 0.13-micron technology in Dresden. Thus, the introduction of x86-64 technology goes as scheduled: AMD was going to start ClawHammer sampling in the first half-year. The first ClawHammer release in the desktop variant is scheduled to the fourth quarter of this year, and there?s no reason to doubt the reality of these plans. Also, the first ClawHammer samples are reported to be showcased at CeBIT show, which is held in the middle of March in Hanover.
We shall remind, that AMD will introduce a number of improvements in Hammer directed both to support the 64-bit code, and to improve the performance. 8 additional SSE registers and 8 general-purpose registers will be added in Hammer. Simultaneously, all general-purpose registers will be extended to 64 bits. Also, AMD brings out support for SSE2 instructions system and improves prefetching algorithms. The processor will have an integer pipeline lengthened up to 12 stages and 17-stage FPU pipeline, with good scalability for further frequency increase. Also, the CPU will have a built-in one- or two-channel memory controller supporting PC2700 DDR SDRAM.
Thanks to NFS4 for the heads up.
EDIT: As I thought, AMD is further ahead with ClawHammer than just "first silicon."
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