PeterScott
Platinum Member
- Jul 7, 2017
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i explain it simply since you seem hell bent on not understading basic things.
Let s assume that the socket s PIN 1 to PIN 256 are used for the RAM signals.
In TR1 the organic (or ceramic) interface below the two dies has 2 X 64 copper traces that get from each die to the relevant pins, all they need to do is to route 64 pins to each of the four dies, that is, seen from the MB the exact connected IMCs are invisible, first die will have a single IMC connected to pin 1-64, second die to pin 65-128 and so on...
That s really no rocket science here....
Yes, but that is 128+ traces that would have to be moved into non optimal locations which is obviously re-wiring the package, which you claimed it was "wired the same way", which clearly it would NOT be. When you start out stating incorrect things, the opposite of reality actually, then your clarity is less than mud.
And beyond that you have the issues I stated, with the loss of manufacturing flexibility.
Time will tell which option AMD chose. Manufacturing simplicity and flexibility, or higher performance. Don't underestimate the importance of manufacturing flexibility.