johnhodgemanisback

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  1. Eug

    Discussion Apple Silicon M series thread

    M1 5 nm Unified memory architecture - LP-DDR4 16 billion transistors 8-core CPU 4 high-performance cores 192 KB instruction cache 128 KB data cache Shared 12 MB L2 cache 4 high-efficiency cores 128 KB instruction cache 64 KB data cache Shared 4 MB L2 cache (Apple claims the 4 high-effiency...
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