I have a i7 920 (1366) and the cache structure (according to CPU-Z) looks like this:
L1 Data 4 x 32 KBytes , 8-way
L1 Inst. 4 x 32 KBytes , 4-way
L2 4 x 256 KBytes , 8-way
L3 8 MBytes, 16-way
And I was wondering if I would to disable half the cores (2 out of 4) would the remaining cores...