Recent content by Zladimir

Thats pretty interesting. Thanks for the mind. There was a flaw in the earlier microcodes. Thats why the TDP Limit bypass works in the first place. Further it means they could correct it software wise. So there is some hidden code, which we didnt understand yet, to influence that calculation. If...

Thank you! When I have time I look into it. For me it did not solve the bug. Anyway its not only the BSOD you will face problems with. See above mentioned bugs. Much earlier post in this thread already discussed this issue and suggestions kept disabling C3. However as you already said, most of...

Both C3 and C6 (and their package state limits) are broken. Both should be disabled and can lead to a lockup. You can read about it in the Intel Whitepapers. https://www.intel.com/content/dam/www/public/us/en/documents/specification-updates/xeon-e5-v3-spec-update.pdf See HSE20, HSE 25 and...

Not necessarily, cause the question is different. Its more like, how well is the voltage curve of Intel ? And as second, if we use adaptive undervolt and lower it too much, do we get instability for high, medium or low core load, or for the load switch ? No one can tell this. But all of them are...

Did anyone tried to use fixed core voltage instead of core voltage offset, and if so how are the results ?

I found out something new. Might be interesting for you. So as many people observed, running inside of OS without microcode your cpu utilizes a higher multiplier, yes ? Probably, we all wondered why. So if you start Windows with OS-microcode also start hwinfo64 und stress all your cores...

Does anyone know how CPU / OS decides if to use "per core boost" or "all core boost" ? Testing with Prime95 using torture 3 threads CPU runs in per core boost, but once I switch over to 4 threads CPU prefers to use all core boost. That is quite inefficient as with 4 threads in per core boost he...

Someone knows of a method to spoof particular core-VID readings ?

Interesting, did you tried with or without disabled vcoms ? @Dufus, might it be possible that setting vcom/fivr faults is per domain, or is it global ? Im actually not home, so I cant test it out. Anyway did you made different observation with FIVR fault/efficiency disabled ? Dufus thanks for...

I tried, you were right. I hit the 180W. However stragenly hot production was a lot less. In average my CPU kept 8°C cooler than stresstest by Prime95 (which hits only 160W). However heat waste is fully absorbed by my oil bath cooling :D From what I recall in electrical sheets Haswell has an...

@Dufus, I could follow you here on 603. Interesting. I am a bit surprised your CPU consumes so much power. Got my 2686v3 (same TDP) on 160W in AVX2 with stable x31 Multi. Are you experiencing an vcore throttle ? Im pretty sure mine is much lower. Need to check that tomorrow. From what I recall...

@kjboughton No the reduction itself of VCCin did not faked the CPU Package Power. Disabling SVID comm's in combination with locking VCCin into fixed mode did the trick. Dufus already told so and the functionality of Throttlestop does exactly this, as I could follow the thread correctly (+600...

@Dufus, I experimented with MSR 0x1AA now. Did not made any difference whatever bit I set. However I locked SVID like you said and it worked. Now I've constant faked cpu package power draw. Thanks again!

'Cause it makes no difference if you enforce uncore update. By my observation uncore neither makes a difference in maximum frequency nore in average. In fact it shouldnt even matter in overall performance in an Intel cpu. The C-state jumping happens in picoseconds, but is an important(!) Intel...

In fact, I didnt claim that. However, your pictures sadly doesnt include a long run to see level TDPs.